參數(shù)資料
型號(hào)： 78Q2133/F
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/38頁(yè)
文件大小： 0K
描述： TXRX 10/100 MDIX 3.3V IND 32-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 490
類型： PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： IEEE 802
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 管件
DS_21x3_001
78Q2123/78Q2133 Data Sheet
Rev. 1.6
11
2
Pin Description
2.1
Legend
Type
Description
Type
Description
A
Analog Pin
CI
TTL-level Input
CIU
TTL-level Input with Pull-up
CIO
TTL-compatible Bi-directional Pin
CIS
TTL-level Input with Schmitt Trigger
COZ
Tristate-able CMOS Output
CO
CMOS Output
S
Supply
G
Ground
2.2
MII (Media Independent Interface)
Signal
Pin
Type
Description
TX_CLK
15
COZ
TRANSMIT CLOCK: TX_CLK is a continuous clock, which provides a
timing reference for the TX_EN, TX_ER and TXD[3:0] signals from the
MAC. The clock frequency is 25 MHz in 100BASE-TX mode and 2.5 MHz
in 10BASE-T mode. This pin is tri-stated in isolate mode and the TXHIM
mode.
TX_EN
16
CI
TRANSMIT ENABLE: TX_EN is asserted by the MAC to indicate that
valid data for transmission is present on the TXD[3:0] pins.
TXD[3:0]
[20:17]
CI
TRANSMIT DATA: TXD[3:0] receives data from the MAC for transmission
on a nibble basis. This data is captured on the rising edge of TX_CLK
when TX_EN is high.
TX_ER
14
CI
TRANSMIT ERROR: TX_ER is asserted high by the MAC to request that
an error code-group be transmitted when TX_EN is high. In PCS bypass
mode, this pin becomes the MSB of the transmit 5-bit code group.
CRS
22
COZ
CARRIER SENSE: When the 78Q2123/78Q2133 are not in repeater
mode, CRS is high whenever a non-idle condition exists on either the
transmitter or the receiver. In repeater mode, CRS is only active when a
non-idle condition exists on the receiver. This pin is tri-stated in isolate
mode.
COL
21
COZ
COLLISION: COL is asserted high when a collision has been detected on
the media. In 10BASE-T mode COL is also used for the SQE test function.
This pin is tri-stated in isolate mode. During half duplex operation, the
rising edge of COL will occasionally occur upon the rising edge of
TX_CLK.
RX_CLK
12
COZ
RECEIVE CLOCK: RX_CLK is a continuous clock, which provides a
timing reference to the MAC for the RX_DV, RX_ER and RXD[3:0] signals.
The clock frequency is 25 MHz in 100BASE-TX mode and 2.5 MHz in
10BASE-T mode. To reduce power consumption in 100BASE-TX mode,
the 78Q2123/78Q2133 provide an optional mode, enabled through
MR16.0, in which RX_CLK is held inactive (low) when no receive data is
detected. This pin is tri-stated in isolate mode.
RX_DV
11
COZ
RECEIVE DATA VALID: RX_DV is asserted high to indicate that valid
data is present on the RXD[3:0] pins. In 100BASE-TX mode, it transitions
high with the first nibble of the preamble and is pulled low when the last
data nibble has been received. In 10BASE-T mode it transitions high when
the start-of-frame delimiter (SFD) is detected. This pin is tri-stated in
isolate mode.
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