參數(shù)資料
型號(hào): 79RC32334-133BBGI
廠(chǎng)商: Integrated Device Technology, Inc.
英文描述: IDT Interprise Integrated Communications Processor
中文描述: IDT的洽談會(huì)集成通信處理器
文件頁(yè)數(shù): 8/30頁(yè)
文件大?。?/td> 467K
代理商: 79RC32334-133BBGI
8 of 30
August 31, 2004
IDT 79RC32334—Rev. Y
sdram_cas_n
Output
H
High
SDRAM CAS Negated
SDRAM mode: Provides SDRAM CAS control signal to all SDRAM banks.
sdram_we_n
Output
H
High
SDRAM WE Negated
SDRAM mode: Provides SDRAM WE control signal to all SDRAM banks.
sdram_cke
Output
H
High
SDRAM Clock Enable
SDRAM mode: Provides clock enable to all SDRAM banks.
sdram_cs_n[3:0]
Output
H
High
SDRAM Chip Select Negated Bus
Recommend external pull-up.
SDRAM mode: Provides chip select to each SDRAM bank.
SODIMM mode: Provides upper select byte enables [7:4].
sdram_s_n[1:0]
Output
H
High
SDRAM SODIMM Select Negated Bus
SDRAM mode: Not used.
SDRAM SODIMM mode: Upper and lower chip selects.
sdram_bemask_n
[3:0]
Output
H
High
SDRAM Byte Enable Mask Negated Bus (DQM)
SDRAM mode: Provides byte enables for each byte lane of all DRAM banks.
SODIMM mode: Provides lower select byte enables [3:0].
sdram_245_oe_n
Output
H
Low
SDRAM FCT245 Output Enable Negated
Recommend external pull-up.
SDRAM mode: Controls output enable to optional FCT245 transceiver bank by asserting during both
reads and writes to any DRAM bank.
sdram_245_dt_r_n
Output
Z
High
SDRAM FCT245 Direction Transmit/Receive
Recommend external pull-up.
Uses cpu_dt_r_n. See CPU Core Specific Signals below.
On-Chip Peripherals
dma_ready_n[1:0] /
dma_done_n[1:0]
I/O
Z
Low
DMA Ready Negated Bus
Requires external pull-up.
Ready mode: Input pin for each general purpose DMA channel that can initiate the next datum in the cur-
rent DMA descriptor frame.
Done mode: Input pin for each general purpose DMA channel that can terminate the current DMA descrip-
tor frame.
dma_ready_n[0] 1st Alternate function PIO[1]; 2nd Alternate function: dma_done_n[0].
dma_ready_n[1] 1st Alternate function PIO[0]; 2nd Alternate function: dma_done_n[1].
pio[15:0]
I/O
See
related
pins
Low
Programmable Input/Output
General purpose pins that can each be configured as a general purpose input or general purpose output.
These pins are multiplexed with other pin functions:
uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0], pci_gnt_n[1], spi_mosi, spi_miso, spi_sck,
spi_ss_n, uart_rx[0], uart_tx[0], uart_rx[1], uart_tx[1], timer_tc_n[0], dma_ready_n[0], dma_ready_n[1].
Note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. The others
default to inputs.
timer_tc_n[0] /
timer_gate_n[0]
I/O
Z
Low
Timer Terminal Count Overflow Negated
Terminal count mode (timer_tc_n): Output indicating that the timer has reached its count compare value
and has overflowed back to 0.
Gate mode (timer_gate_n): input indicating that the timer may count one tick on the next clock edge.
1st Alternate function: PIO[2].
2nd Alternate function: timer_gate_n[0].
uart_rx[1:0]
I/O
Z
Low
UART Receive Data Bus
UART mode: Each UART channel receives data on their respective input pin.
uart_rx[0] Alternate function: PIO[6].
uart_rx[1] Alternate function: PIO[4].
Name
Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Description (Part 4 of 7)
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79RC32334-133BBI IDT Interprise Integrated Communications Processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
79RC32334-133BBI 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BB 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BBG 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BBGI 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor
79RC32334-150BBI 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:IDT Interprise Integrated Communications Processor