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IDT Interrupt Controller
Interrupt Status Description
79RC32438 User Reference Manual
8 - 5
November 4, 2002
Notes
Bit
Interrupt/Status Description
Refer to
0
DMA Channel 0.
OR of the bits in the DMA0S not masked by DMA0SM.
Chapter 9
1
DMA Channel 1.
OR of the bits in the DMA1S not masked by DMA1SM.
Chapter 9
2
DMA Channel 2.
OR of the bits in the DMA2S not masked by DMA2SM.
Chapter 9
3
DMA Channel 3.
OR of the bits in the DMA3S not masked by DMA3SM.
Chapter 9
4
DMA Channel 4.
OR of the bits in the DMA4S not masked by DMA4SM.
Chapter 9
5
DMA Channel 5.
OR of the bits in the DMA5S not masked by DMA5SM.
Chapter 9
6
DMA Channel 6.
OR of the bits in the DMA6S not masked by DMA6SM.
Chapter 9
7
DMA Channel 7.
OR of the bits in the DMA7S not masked by DMA7SM.
Chapter 9
8
DMA Channel 8.
OR of the bits in the DMA8S not masked by DMA8SM.
Chapter 9
9
DMA Channel 9.
OR of the bits in the DMA9S not masked by DMA9SM.
Chapter 9
10
-
31 Reserved
Table 8.3 IPEND3 Interrupt Source Description
Bit
Interrupt/Status Description
Refer to
0
UART General Interrupt 0
.
Chapter 13
1
UART TXRDY 0 Interrupt
.
Chapter 13
2
UART RXRDY 0 Interrupt
.
Chapter 13
3
UART General Interrupt 1
.
Chapter 13
4
UART TXRDY 1 Interrupt
.
Chapter 13
5
UART RXRDY 1 Interrupt
.
Chapter 13
6
PCI Interrupt
. OR of bits in PCIS not masked by PCISM.
Chapter 10
7
PCI Decoupled Access Interrupt.
OR of bits in the PCIDAS register not masked by
PCIDASM.
Chapter 10
8
SPI Interrupt.
Corresponds to SPIF and MODF bits in the SPS register.
Chapter 16
9
Device Decoupled Operation Done.
Corresponds to the F bit in the DEVDACS regis-
ter.
Chapter 6
10
I2C-bus Master Interface Interrupt
. OR of bits in I2CMS not masked by I2CMSM.
Chapter 15
11
I2C-bus Slave Interface Interrupt
. OR of bits in I2CSS not masked by I2CSSM.
Chapter 15
12
Ethernet 0 Input FIFO Overflow
. Corresponds to OVR bit in ETH0INTFC register.
Chapter 11
13
Ethernet 0 Output FIFO Underflow
. Corresponds to UND bit in ETH0INTFC register. Chapter 11
14
Ethernet 0 Pause Frame Done.
Corresponds to PFD bit in ETH0OS register.
Chapter 11
15
Ethernet 1 Input FIFO Overflow
. Corresponds to OVR bit in ETH1INTFC register.
Chapter 11
16
Ethernet 1 Output FIFO Underflow
. Corresponds to UND bit in ETH1INTFC register. Chapter 11
17
Ethernet 1 Pause Frame Done.
Corresponds to PFD bit in ETH1OS register.
Chapter 11
18-31 Reserved
Table 8.4 IPEND5 Interrupt Source Description