IDT Table of Contents
79RC32438 User Reference Manual
vii
November 4, 2002
Notes
PCI Target Control Register...........................................................................................10-38
Transaction Ordering...............................................................................................................10-39
PCI Messaging Unit.................................................................................................................10-40
PCI Inbound Message [0|1] Register.............................................................................10-41
PCI Outbound Message [0|1] Register...........................................................................10-41
PCI Inbound Doorbell Register ......................................................................................10-42
PCI Inbound Interrupt Cause Register...........................................................................10-42
PCI Inbound Interrupt Mask Register.............................................................................10-43
PCI Outbound Doorbell Register....................................................................................10-44
PCI Outbound Interrupt Cause Register........................................................................10-44
PCI Outbound Interrupt Mask Register..........................................................................10-45
PCI Configuration Registers....................................................................................................10-45
Vendor ID Register.........................................................................................................10-47
Device ID Register.........................................................................................................10-47
Command Register........................................................................................................10-47
Status Register...............................................................................................................10-49
Device Revision ID Register...........................................................................................10-51
Class Code Register......................................................................................................10-51
Cache Line Size Register...............................................................................................10-51
Master Latency Register................................................................................................10-52
Header Type Register....................................................................................................10-52
BIST Register.................................................................................................................10-53
PCI Base Address [0|1|2|3] Register..............................................................................10-53
Subsystem Vendor ID ....................................................................................................10-54
Subsystem ID Register ..................................................................................................10-54
Interrupt Line Register....................................................................................................10-55
Interrupt Pin Register.....................................................................................................10-55
Minimum Grant Register................................................................................................10-55
Maximum Latency Register............................................................................................10-56
Target Ready Time-out Register ....................................................................................10-56
Retry Limit Register........................................................................................................10-57
PCI Base Address [0|1|2|3] Control ...............................................................................10-57
PCI Base Address [0|1|2|3] Mapping Register...............................................................10-59
PCI Management Register.............................................................................................10-60
11 Ethernet Interfaces
Introduction................................................................................................................................11-1
Features.....................................................................................................................................11-1
Block Diagram ...........................................................................................................................11-1
Functional Overview..................................................................................................................11-1
Input and Output FIFOs.............................................................................................................11-2
Ethernet Register Description....................................................................................................11-2
Ethernet Interface Control Register..................................................................................11-5
Ethernet FIFO Transmit Threshold Register....................................................................11-7
Address Recognition Logic........................................................................................................11-7
Ethernet Address Recognition Control Register...............................................................11-9
Ethernet Hash Table [0|1] Register................................................................................ 11-11
Ethernet Station Address [0|1|2|3] Low Register ........................................................... 11-11
Ethernet Station Address [0|1|2|3] High Register...........................................................11-12