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IDT MIPS32 4Kc Processor Core
Memory Management
79RC32438 User Reference Manual
2 - 32
November 4, 2002
Notes
Figure 2.26 shows a flow diagram of the 4Kc core address translation process. The top portion of the
figure shows a virtual address for a 4-KByte page size. The width of the Offset is defined by the page size.
The remaining 20 bits of the address represent the virtual page number (VPN), that index the 1M-entry
page table.
The bottom portion of Figure 2.26 shows the virtual address for a 16-MByte page size. The remaining 8
bits of the address represent the VPN, that index the 256-entry page table.
Figure 2.26 32-bit Virtual Address Translation
Hits, Misses, and Multiple Matches
Each JTLB entry contains a tag and two data fields. If a match is found, the upper bits of the virtual
address are replaced with the page frame number (PFN) stored in the corresponding entry in the data array
of the JTLB. The granularity of JTLB mappings is defined in terms of TLB pages. The 4Kc core JTLB
supports pages of different sizes ranging from 4 KB to 16 MB in powers of 4. If a match is found, but the
entry is invalid (i.e., the V bit in the data field is 0), a TLB Invalid exception is taken.
If no match occurs (TLB miss), an exception is taken and software refills the TLB from the page table
resident in memory. Figure 2.27 show the translation and exception flow of the TLB.
Software can write over a selected TLB entry or use a hardware mechanism to write into a random entry.
The Random register selects which TLB entry to use on a TLBWR. This register decrements almost every
cycle, wrapping to the maximum once it’s value is equal to the Wired register. Thus, TLB entries below the
Wired value cannot be replaced by a TLBWR allowing important mappings to be preserved. In order to
reduce the possibility for a livelock situation, the Random register includes a 10b LFSR that introduces a
pseudo-random perturbation into the decrementing.
The 4Kc core implements a TLB write-compare mechanism to ensure that multiple TLB matches do not
occur. On the TLB write operation, the VPN2 field to be written is compared with all other entries in the TLB.
If a match occurs, the 4Kc core takes a machine-check exception, sets the TS bit in the CP0 Status register,
and aborts the write operation. For additional information on exceptions, see the Exceptions section later in
this chapter. There is a hidden bit in each TLB entry that is cleared on a ColdReset. This bit is set once the
TLB entry is written and is included in the match detection. Therefore, uninitialized TLB entries will not
cause a TLB shutdown.
11
Virtual address with 1M (2
20
) 4-KByte pages
20 bits = 1M pages
VPN
Virtual Address with 256 (2
8
)16-MByte pages
8 bits = 256 pages
Virtual-to-physical
Bit 31 of the virtual address
selects user and kernel
address spaces.
Offset passed unchanged to
physical memory.
Virtual-to-physical
translation in TLB
Offset passed unchanged to
physical memory.
32-bit Physical Address
ASID
Offset
PFN0/1
Offset
TLB
TLB
ASID
VPN
Offset
0
23
31
32
24
39
31
32
39
0
12
0
31
8
8
24
8
20
12