IDT PCI Bus Interface
PCI Master
79RC32438 User Reference Manual
10 - 19
November 4, 2002
Notes
All IPBus initiated I/O read transactions translate into single data phase PCI transactions even if a burst
transaction was generated on the IPBus (i.e., bursts are not supported).
I/O Write
All IPBus write transactions whose address matches the base address in a PCI Local Base Address
(PCILBAx) register configured for I/O space (i.e., the MSI bit is set in the corresponding PCI Local Base
Address Control (PCILBAxC) register) result in an I/O write transaction on the PCI bus.
The value in the corresponding PCI Local Base Address Map (PCILBAxM) register maps the upper bits
of the local IPBus address, as indicated by the SIZE field of the PCILBAxC register, to the PCI I/O read
address.
The value written on the PCI bus corresponds to the data value of the IPBus write transaction. The byte
enables on the PCI bus correspond to the size/byte enables of the IPBus write operation (i.e., byte, half-
word, triple-byte, or word).
IPBus initiated I/O write transactions may contain one or more data phases (i.e., bursts are supported).
Memory Read
An IPBus read transaction will result in a memory read transaction on the PCI Bus when the following
conditions are met:
–
The address matches the base address in a PCI Local Base Address (PCILBAx) register that is
configured for memory space (i.e., the MSI bit is cleared in the corresponding PCI Local Base
Address Control (PCILBAxC) register)
–
Read Transaction (RT bit in corresponding PCILBAxC) bit is cleared, resulting in a memory read
transaction on the PCI bus.
The value in the corresponding PCI Local Base Address Map (PCILBAxM) register maps the upper bits
of the local IPBus address, as indicated by the SIZE field of the PCILBAxC register, to the PCI memory read
address.
The byte enables on the PCI bus correspond to the size/byte enables of the IPBus read operation (i.e.,
byte, halfword, triple-byte, or word).
Memory Write
All IPBus write transactions whose address matches the base address in a PCI Local Base Address
(PCILBAx) register that is configured for memory space (i.e., the MSI bit is cleared in the corresponding PCI
Local Base Address Control (PCILBAxC) register) result in a memory write transaction on the PCI bus.
The value in the corresponding PCI Local Base Address Map (PCILBAxM) register maps the upper bits
of the local IPBus address, as indicated by the SIZE field of the PCILBAxC register, to the PCI memory
write address.
The value written on the PCI bus corresponds to the data value of the IPBus write transaction. The byte
enables on the PCI bus correspond to the size/byte enables of the IPBus write operation (i.e., byte, half-
word, triple-byte, or word).
The PCI bus interface will attempt to perform burst PCI memory write transactions whenever possible.
The PCI interface will add a data phase to the memory write transaction in progress if:
–
Data exists in the CPU master output FIFO whose address is equal to that of the current data
quantity being transferred plus four
–
The Master Latency Timer has not expired.
Configuration Read
To generate a PCI configuration read transaction, an IPBus master (e.g., CPU core) writes the desired
configuration register address to the PCI Configuration Address (PCICFGA) register and performs a read
from the PCI Configuration Data (PCICFGD) register. The value returned to the IPBus master will be that