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IDT EJTAG System
Hardware Breakpoints
79RC32438 User Reference Manual
20 - 39
November 4, 2002
Notes
Data breakpoints depend on endianess, because values on the byte lanes are used in the equations.
Thus it is required that the debug software programs the breakpoints accordingly to endianess. It is imple-
mentation dependent for a data breakpoint to match when the memory system does not ever respond to the
data access or generates a bus error from a system watchdog. If no match occurs, then the processor
hangs without the data breakpoint generating a debug exception or trigger.
Data Breakpoints in case of Unaligned Address
Unaligned addresses can result from explicit halfword, word, and doubleword accesses (for example, if
an effective address of 0x01 is used as source of a Load Halfword (LH) instruction). The ADDR used in the
comparison is the effective address. The BYTELANE value is defined according to Table 20.24 for a 32-bit
processor.
With the above well-defined values of BYTELANE, the behavior is well-defined for data breakpoints
without value compares on operations with unaligned addresses. The BLM field in the DBCn register can
be used to avoid value compares if all BLM bits are set to 1. If the data breakpoint depends on a value
compare, then loads will cause an Address Error exception, and for stores the data value (DATA) is
UNPREDICTABLE. This UNPREDICTABLE data can cause match of a data breakpoint on a store, but an
implementation can choose never to indicate a match on data breakpoints depending on value compare if
having unaligned address.
If a debug exception is taken on the store then the debug handler can investigate the processor state
and thereby determine if the address was unaligned and UNPREDICTABLE store data for the memory
access thereby caused the debug exception. If a debug exception is not taken for the store, then an
Address Error exception is taken. So, in both cases it is possible for debug software to detect the bug. The
BLM field in the DBCn register can be used to avoid compare on UNPREDICTABLE data, in case all of the
BLM bits are set to 1.
If the data breakpoint is used as a triggerpoint, a BS bit might be set after a compare with UNPREDICT-
ABLE data; however, an Address Error exception occurs in this case thereby making it possible to detect
the bug.
Match for Data Breakpoint with Value Compare on Bus or Cache Error
If a data value compare is required to evaluate a data breakpoint, the DB_no_value_compare equation
is false (see section “Conditions for Matching Data Breakpoints” on page 20-37). However, if a bus or cache
error occurs on the load, then there is no valid data to use in the compare. This case has two possibilities:
The match will fail.
The match will compare on invalid data, and then indicate a pending bus or cache error through the
DBusEP or CacheEP bits in the Debug register, if a debug exception is taken. This occurrence
might cause a trigger indication to be set on the compare with invalid data.
A bus or cache error on a store does not affect the data breakpoint compare.
Refer to section “Data Breakpoint Compare on Invalid Data” on page 20-52for recommendations on
implementing data breakpoint compares on invalid data.
Size
ADDR
BYTELANE[3:0]
[2]
[1]
[0]
Little Endian
Big Endian
Halfword
x
1
1.
x = Don’t care
0
x
0011
2
1100v
x
1
x
1100
2
0011
2
Word
x
x
x
1111
2
Table 20.24 BYTELANE at Unaligned Address for 32-bit Processors