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IDT Clocking and Initialization
Reset Register Description
79RC32438 User Reference Manual
3 - 3
November 4, 2002
Notes
Reset Register Description
Reset and Initialization
The RC32438 may be reset with either a warm reset or a cold reset.
Cold Reset
A cold reset is initiated through the assertion of the cold reset (COLDRSTN) pin. The COLDRSTN pin is
typically asserted by an external voltage monitor or reset switch at power-up. A cold reset causes the
RC32438 to initialize its internal state, assert the reset (RSTN) bidirectional pin, assert the BOEN pin, and
assert the BDIRN pin. No state information of any kind is preserved. Figure 3.3 shows a cold reset.
Using the boot configuration vector the internal phase lock loop locks onto the master clock input (CLK)
and generates the CPU pipeline clock (PCLK) and the IPBus clock (ICLK). When the COLDRSTN signal is
negated, the boot configuration vector is obtained from the bottom 16-bits of the data bus (MDATA[15:0]
clocked in on the previous rising edge of CLK).
1
Once the processor clock stabilizes, the RSTN pin is tri-stated. The RC32438 then waits an additional
4096 master clock cycles to allow the RSTN pin to be pulled up by an external resistor, then samples the
state of the RSTN pin and the PCIRSTN pin if the PCI interface is selected to operate in satellite mode by
the boot configuration vector. If RSTN is negated and if the PCI interface is selected to operate in satellite
mode the de-glitched PCIRSTN signal is also negated, then the CPU begins execution by taking a MIPS
soft reset exception. If RSTN is still asserted, the RC32438 waits an additional 4096 master clock cycles
and repeats the above process. If the PCI interface is selected to operate in satellite mode and the de-
glitched PCIRSTN signal is asserted, then the RC32438 remains in a reset state until it is negated (or until
COLDRSTN or RSTN is asserted at which point a cold or warm reset process begins).
Before the boot configuration vector has been read during a cold reset, the external clock (EXTCLK) pin
output is held low. Within 16 CLK clock cycles of reading the boot configuration vector, the RC32438 will
begin generating EXTCLK. EXTCLK is guaranteed to be glitch free and maintain a 60/40 duty cycle.
Register Offset
1
1.
The address of the register is equal to the register offset added to the base value of 0x1800_0000.
2.
Note that the CEA register is discussed in Chapter 4, System Integrity Functions.
Register Name
Register Function
Size
0x00_8000
RESET
Reset
32-bit
0x00_8004
BVC
Boot configuration vector
32-bit
0x00_8008
CEA
CPU error address
32-bit
0x00_800C through 0x00_FFFF
Reserved
Table 3.2 Reset Register Map
1.
The CPU pipeline clock multiplier field (i.e., MDATA[3:0]) should be driven to a valid value as soon as possible
after power stabilizes. This field is use by the PLL before COLDRSTN is negated. All other fields of the boot
configuration vector are sampled only when COLDRSTN is negated.