參數(shù)資料
型號： 80960RM
廠商： Intel Corp.
英文描述： 80960RM I/O Processor(80960RM I/O 處理器)
中文描述： 80960RM I / O處理器（80960RM的I / O處理器）
文件頁數(shù)： 12/54頁
文件大?。?/td> 855K
代理商： 80960RM
80960RM
—
Data Sheet
12
Advance Information
2.2.1
Burst Bus
A 32-bit high-performance bus controller interfaces the 80960RM processor to the Bus Interface
Unit. The Bus Control Unit fetches instructions and transfers data on the internal bus at the rate of
up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed.
Data caching is programmed through a group of logical memory templates and a defaults register.
The Bus Control Unit
’
s features include:
Multiplexed external bus minimizes pin count
External ready control for address-to-data, data-to-data and data-to-next-address wait state types
Little endian byte ordering
Unaligned bus accesses performed transparently
Three-deep load/store queue decouples the bus from the 80960 core
Upon reset, the 80960JT conducts an internal self test. Before executing its first instruction, it performs an
external bus confidence test by performing a checksum on the first words of the Initialization Boot Record.
2.2.2
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed through the Timer Unit registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960JT
’
s interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected.
2.2.3
Priority Interrupt Controller
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960JT exploits several techniques to minimize latency:
Interrupt vectors and interrupt handler routines can be reserved on-chip
Register frames for high-priority interrupt handlers can be cached on-chip
The interrupt stack can be placed in cacheable memory space
2.2.4
Faults and Debugging
The 80960JT employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. With software, the 80960JT may be configured
to detect as many as seven different trace event types. Alternatively,
mark
and
fmark
instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.2.5
On-Chip Cache and Data RAM
Memory subsystems often impose substantial wait state penalties. The 80960JT integrates
considerable storage resources on-chip to decouple CPU execution from the external bus. The
80960JT includes a 16 Kbyte instruction cache, a 4 Kbyte data cache and 1 Kbyte data RAM.
相關(guān)PDF資料
PDF描述
80960RN 80960RN I/O Processor(80960RN I/O 處理器)
80960SA Embedded 32-Bit Microprocessor With 16-Bit Burst Data Bus(帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式 32-BIT微處理器)
80960SB Embedded 32-Bit Microprocessor With 16-Bit Burst Data Bus(帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式 32-BIT微處理器)
8097JF COMMERCIAL/EXPRESS HMOS MICROCONTOLLER
8098 COMMERCIAL/EXPRESS HMOS MICROCONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
80960SA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
80960SB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
80961-01 制造商:Glenair 功能描述:EARTH BOND M10 FOR AL 4MM T
809621-000 制造商:TE Connectivity 功能描述:809621-000
80963 制造商:3M Electronic Products Division 功能描述:Tape Temflex 1500 Brown 15mmx10m
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