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參數(shù)資料
| 型號： | 80960RM |
| 廠商： | Intel Corp. |
| 英文描述： | 80960RM I/O Processor(80960RM I/O 處理器) |
| 中文描述： | 80960RM I / O處理器（80960RM的I / O處理器） |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 855K |
| 代理商： | 80960RM |
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80960RM
—
Data Sheet
22
Advance Information
Table 7.
Secondary PCI Bus Signals
NAME
COUNT
TYPE
DESCRIPTION
S_AD[31:0]
32
I/O
5V
Sync(P)
Srst(0)
SECONDARY PCI ADDRESS/DATA
is the multiplexed secondary PCI bus.
S_PAR
1
I/O
Sync(P)
Srst(0)
SECONDARY PCI BUS PARITY
is even parity across
S_AD[31:0]
and
S_C/BE[3:0]#
.
S_C/BE[3:0]#
4
I/O
5V
Sync(P)
Srst(0)
SECONDARY PCI BUS COMMAND and BYTE ENABLES
are
multiplexed on the same PCI pins. During the address phase, they
define the bus command. During the data phase, they are used as the
byte enables for
S_AD[31:0]
.
S_FRAME#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS CYCLE FRAME
is asserted to indicate the
beginning and duration of an access.
S_IRDY#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS INITIATOR READY
indicates the initiating
agent
’
s ability to complete the current data phase of the transaction.
During a write, it indicates that valid data is present on the secondary
Address/Data bus. During a read, it indicates the processor is ready to
accept the data.
S_TRDY#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS TARGET READY
indicates the target agent
’
s
ability to complete the current data phase of the transaction. During a
read, it indicates that valid data is present on the secondary Address/Data
bus. During a write, it indicates the target is ready to accept the data.
S_STOP#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS STOP
indicates a request to stop the current
transaction on the secondary PCI bus.
S_DEVSEL#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS DEVICE SELECT
is driven by a target agent
that has successfully decoded the address. As an input, it indicates
whether or not an agent has been selected.
S_SERR#
1
I/O
5V
OD
Sync(P)
Srst(Z)
SECONDARY PCI BUS SYSTEM ERROR
is driven for address parity
errors on the secondary PCI bus.
S_RST#
1
O
Asyn
SECONDARY PCI BUS RESET
is an output based on
P_RST#
. It brings
PCI-specific registers, sequencers, and signals to a consistent state.
When
P_RST#
is asserted or BCR[6] is set, it causes
S_RST#
to assert
and:
PCI output signals are driven to a known consistent state.
PCI bus interface output signals are three-stated.
open drain signals such as
S_SERR#
are floated
S_RST#
may be asynchronous to
P_CLK
when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
S_PERR#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS PARITY ERROR
is asserted when a data parity
error during a secondary PCI bus transaction.
S_LOCK#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS LOCK
indicates the need to perform an atomic
operation on the secondary PCI bus.
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