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參數(shù)資料
| 型號(hào)： | 82845G |
| 廠商： | INTEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA760 |
| 封裝： | 37.50 X 37.50 MM, 1 MM PITCH, FLIP CHIP, BGA-760 |
| 文件頁數(shù)： | 25/193頁 |
| 文件大?。?/td> | 2990K |
| 代理商： | 82845G |
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Intel
82845G/82845GL/82845GV GMCH Datasheet
25
Signal Description
2.2
Memory Interface
2.2.1
DDR SDRAM Interface
Signal Name
Type
Description
SCMDCLK_[5:0]
O
SSTL_2
Differential DDR Clock:
SCMDCLK and SCMDCLK# pairs are differential
clock outputs. The crossing of the positive edge of SCMDCLK and the
negative edge of SCMDCLK# is used to sample the address and control
signals on the SDRAM. There are 3 pairs to each DIMM.
SCMDCLK_[5:0]#
O
SSTL_2
Complementary Differential DDR Clock:
These are the complementary
Differential DDR Clock signals.
SCS_[3:0]#
O
SSTL_2
Chip Select:
These signals select particular SDRAM components during
the active state. There is one SCS# for each SDRAM row, toggled on the
positive edge of SCMDCLK.
SMAA_[12:0],
SMAB_[5,4,2,1]
O
SSTL_2
Memory Address:
These signals provide the multiplexed row and column
address to the SDRAM. SMAB_[5,4,2,1] signals are selective CPC signals
and are identical to SMAA_[5,4,2,1].
SBA[1:0]
O
SSTL_2
Bank Select (Bank Address):
These signals define which banks are
selected within each SDRAM row. Bank select and memory address signals
combine to address every possible location within an SDRAM device.
SRAS#
O
SSTL_2
Row Address Strobe:
SRAS# is used with SCAS# and SWE# (along with
SCS#) to define the SDRAM commands.
SCAS#
O
SSTL_2
Column Address Strobe:
SCAS# is used with SRAS# and SWE# (along
with SCS#) to define the SDRAM commands.
SWE#
O
SSTL_2
Write Enable:
SWE# is used with SCAS# and SRAS# (along with SCS#) to
define the SDRAM commands.
SDQ_[63:0]
I/O
SSTL_2
Data Lines:
SDQ_[63:0] interface to the SDRAM data bus.
SDM_[7:0]
O
SSTL_2
Data Mask:
When activated during writes, the corresponding data groups in
the SDRAM are masked. There is one SDM for every eight data lines. SDM
can be sampled on both edges of the data strobes.
SDQS_[7:0]
I/O
SSTL_2
Data Strobes:
Data strobes are used for capturing data. During writes,
SDQS is centered in data. During reads, SDQS is edge aligned with data.
The following list matches the data strobe with the data bytes.
SDQS_7 = SDQ_[63:56]
SDQS_6 = SDQ_[55:48]
SDQS_5 = SDQ_[47:40]
SDQS_4 = SDQ_[39:32]
SDQS_3 = SDQ_[31:24]
SDQS_2 = SDQ_[23:16]
SDQS_1 = SDQ_[15:8]
SDQS_0 = SDQ_[7:0]
SCKE_[3:0]
O
SSTL_2
Clock Enable:
SCKE is used to initialize DDR SDRAM during power-up and
to place all SDRAM rows into and out of self-refresh during Suspend-to-
RAM. SCKE is also used to dynamically power down inactive SDRAM rows.
There is one SCKE per SDRAM row, toggled on the positive edge of
SCMD_CLK.
SRCVEN_OUT#
O
SSTL_2
Receive Enable Out:
This signal is a feedback testpoint signal used to
enable the DQS input buffers during reads. This pin should be connect to
SRCVEN_IN through an
un-populated
backside resistor site.
SRCVEN_IN#
I
SSTL_2
Receive Enable In:
This signal is a feedback testpoint signal used to
enable the DQS input buffers during reads.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82845GL | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GV | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845Gx | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845Mx | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82845GE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 82845GL | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GV | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
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