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參數(shù)資料
| 型號： | 82845GL |
| 廠商： | INTEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA760 |
| 封裝： | 37.50 X 37.50 MM, 1 MM PITCH, FLIP CHIP, BGA-760 |
| 文件頁數(shù)： | 31/193頁 |
| 文件大?。?/td> | 2990K |
| 代理商： | 82845GL |
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Intel
82845G/82845GL/82845GV GMCH Datasheet
31
Signal Description
2.4.5
PCI Signals–AGP Semantics
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension.
For transactions on the AGP interface carried using PCI protocol, these signals completely
preserve
PCI Local Bus Specification, Revision 2.1
semantics. The exact roles of all PCI signals
during AGP transactions are defined below.
NOTES:
1. PCIRST# from the ICH4 is connected to RSTIN# and is used to reset AGP interface logic within the GMCH.
The AGP agent will also typically use PCIRST# provided by the ICH4 as an input to reset its internal logic.
2. The LOCK# signal is
not
supported on the AGP Interface (even for PCI operations).
3. The PERR# and SERR# signals are
not
supported on the AGP interface.
Signal Name
Type
Description
GFRAME#
I/O s/t/s
AGP
Frame:
GFRAME# is an output from the GMCH during Fast Writes.
GIRDY#
I/O s/t/s
AGP
Initiator Ready:
GIRDY# indicates the AGP compliant master is ready to
provide all write data for the current transaction. Once GIRDY# is asserted for a
write operation, the master is not allowed to insert wait states. The assertion of
GIRDY# for reads indicates that the master is ready to transfer to a subsequent
block (4 clocks) of read data. The master is
never
allowed to insert a wait state
during the initial data transfer (first 4 clocks) of a read transaction. However, it
may insert wait states after each 4 clock block is transferred.
NOTE:
There is no GFRAME# – GIRDY# relationship for AGP transactions.
GTRDY#
I/O s/t/s
AGP
Target Ready:
GTRDY# indicates the AGP compliant target is ready to provide
read data for the entire transaction (when the transfer size is less than or equal
to 4 clocks) or is ready to transfer the initial or subsequent block (four clocks) of
data when the transfer size is greater than four clocks. The target is allowed to
insert wait-states after each block (four clocks) is transferred on both read and
write transactions.
GSTOP#
I/O s/t/s
AGP
Stop:
Same as PCI. Not used by AGP.
GDEVSEL#
I/O s/t/s
AGP
Device Select:
Same as PCI. Not used by AGP.
GREQ#
I
AGP
Request:
Same as PCI. This signal is used to request access to the bus to
initiate a PCI or AGP request.
GGNT#
O
AGP
Grant:
Same meaning as PCI but additional information is provided on
GST[2:0]. The additional information indicates that the selected master is the
recipient of previously requested read data (high or normal priority); it is to
provide write data (high or normal priority), for a previously queued write
command or has been given permission to start a bus transaction (AGP or PCI).
GAD_[31:0]
I/O AGP
Address:
Same as PCI.
GC/BE_[3:0]#
I/O AGP
Command/Byte Enable:
These signals have a slightly different meaning for
AGP. Provides command information (different commands than PCI) when
requests are being queued when using GPIPE#. Provide valid byte information
during AGP write transactions and are not used during the return of read data.
GPAR/
ADD_DETECT
I/O AGP
PAR:
Same as PCI. Not used on AGP transactions but used during PCI
transactions as defined by the
PCI Local Bus Specification, Revision 2.1.
ADD_DETECT:
The 82845G GMCH multiplexes an ADD_DETECT signal with
the GPAR signal on the AGP bus. This signal acts as a strap and indicates
whether the interface is in AGP or DVO mode. The 82845G GMCH has an
internal pull-up on this signal that will naturally pull it high. If an ADD card is
present, the signal will be pulled low on the ADD card and the AGP/DVO
multiplex select bit in the GMCHCFG register will be set to DVO mode.
Motherboards that use this interface in a DVO down scenario (no AGP
connector) should have a pull-down resistor on ADD_DETECT.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82845GV | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845Gx | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845Mx | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MZ | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82845GV | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
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