參數(shù)資料
型號(hào): 82845Gx
廠商: Intel Corp.
英文描述: Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
中文描述: 英特爾82845G/82845GL/82845GV圖形和內(nèi)存控制器中樞(GMCH)
文件頁(yè)數(shù): 65/193頁(yè)
文件大?。?/td> 2990K
代理商: 82845GX
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)當(dāng)前第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)
Intel
82845G/82845GL/82845GV GMCH Datasheet
65
Register Description
At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM
segment must be programmed to be both readable and writeable.
As an example, consider BIOS that is implemented on the expansion bus. During the initialization
process, the BIOS can be shadowed in main memory to increase the system performance. When
BIOS is shadowed in main memory, it should be copied to the same address location. To shadow
the BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed
by first doing a read of that address. This read is forwarded to the expansion bus. The host then
does a write of the same address, which is directed to main memory. After the BIOS is shadowed,
the attributes for that memory area are set to read only so that all writes are forwarded to the
expansion bus.
Figure 3-4
and
Table 3-2
show the PAM registers and the associated attribute bits.
For details on overall system address mapping scheme, refer to
Chapter 5
.
Figure 3-4. PAM Register Attributes
Table 3-2. PAM Register Attributes
PAM Reg
Attribute Bits
Memory Segment
Comments
Offset
PAM0[3:0]
Reserved
90h
PAM0[7:4]
R
R
WE
RE
0F0000h–0FFFFFh
BIOS Area
90h
PAM1[3:0]
R
R
WE
RE
0C0000h–0C3FFFh
ISA Add-on BIOS
91h
PAM1[7:4]
R
R
WE
RE
0C4000h–0C7FFFh
ISA Add-on BIOS
91h
PAM2[3:0]
R
R
WE
RE
0C8000h–0CBFFFh
ISA Add-on BIOS
92h
PAM2[7:4]
R
R
WE
RE
0CC000h–0CFFFFh
ISA Add-on BIOS
92h
PAM3[3:0]
R
R
WE
RE
0D0000h–0D3FFFh
ISA Add-on BIOS
93h
PAM3[7:4]
R
R
WE
RE
0D4000h–0D7FFFh
ISA Add-on BIOS
93h
PAM4[3:0]
R
R
RE
0D8000h–0DBFFFh
ISA Add-on BIOS
94h
PAM4[7:4]
R
R
WE
RE
0DC000h–0DFFFFh
ISA Add-on BIOS
94h
PAM5[3:0]
R
R
WE
RE
0E0000h–0E3FFFh
BIOS Extension
95h
PAM5[7:4]
R
R
WE
RE
0E4000h–0E7FFFh
BIOS Extension
95h
PAM6[3:0]
R
R
WE
RE
0E8000h–0EBFFFh
BIOS Extension
96h
PAM6[7:4]
R
R
WE
RE
0EC000h–0EFFFFh
BIOS Extension
96h
RE
WE
RE
R
R
WE
R
R
7
6
5
4
3
2
1
0
PAM6
PAM5
PAM4
PAM3
PAM2
PAM1
PAM0
Read Enable (R/W)
1=Enable
0=Disable
Write Enable (R/W)
1=Enable
0=Disable
Reserved
Reserved
Read Enable (R/W)
1=Enable
0=Disable
Write Enable (R/W)
1=Enable
0=Disable
Reserved
Reserved
96h
95h
94h
93h
92h
91h
90h
Offset
相關(guān)PDF資料
PDF描述
82845MP Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845Mx Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MZ Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845PE 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
82845GE 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82845MP 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845PE 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
8284611SM 制造商:Thomas & Betts 功能描述: