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參數(shù)資料
| 型號(hào)： | 82C37 |
| 廠商： | Intersil Corporation |
| 英文描述： | IDT INTEGRATED COMM PROCESSOR 32-BIT, 350MHZ |
| 中文描述： | 高性能的CMOS可編程DMA控制器 |
| 文件頁(yè)數(shù)： | 15/23頁(yè) |
| 文件大?。?/td> | 204K |
| 代理商： | 82C37 |
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4-206
82C37A
AC Electrical Specifications
V
CC
= +5.0V
±
10%, GND = 0V, T
A
= 0
o
C to +70
o
C (C82C37A),
T
A
= -40
o
C to +85
o
C (I82C37A),
T
A
= -55
o
C to +125
o
C (M82C37A)
SYMBOL
PARAMETER
82C37A-5
82C37A
82C37A-12
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
DMA (MASTER) MODE
(1)TAEL
AEN HIGH from CLK LOW (S1) Delay
Time
-
175
-
105
-
50
ns
(2)TAET
AEN LOW from CLK HIGH (SI) Delay
Time
-
130
-
80
-
50
ns
(3)TAFAB
ADR Active to Float Delay from CLK
HIGH
-
90
-
55
-
55
ns
(4)TAFC
READ or WRITE Float Delay from
CLK HIGH
-
120
-
75
-
50
ns
(5)TAFDB
DB Active to Float Delay from CLK
HIGH
-
170
-
135
-
90
ns
(6)TAHR
ADR from READ HIGH Hold Time
TCY-100
-
TCY-75
-
TCY-65
-
ns
(7)TAHS
DB from ADSTB LOW Hold Time
TCL-18
-
TCL-18
-
TCL-18
-
ns
(8)TAHW
ADR from WRITE HIGH Hold Time
TCY-65
-
TCY-65
-
TCY-50
-
ns
(9)TAK
DACK Valid from CLK LOW
Delay Time
-
170
-
105
-
69
ns
EOP HIGH from CLK HIGH
Delay Time
-
170
-
105
-
90
ns
EOP LOW from CLK HIGH
Delay Time
-
100
-
60
-
35
ns
(10)TASM
ADR Stable from CLK HIGH
-
110
-
60
-
50
ns
(11)TASS
DB to ADSTB LOW Setup Time
TCH-20
-
TCH-20
-
TCH-20
-
ns
(12)TCH
CLK HIGH Time (Transitions 10ns)
70
-
55
-
30
-
ns
(13)TCL
CLK LOW Time (Transitions 10ns)
50
-
43
-
30
-
ns
(14)TCY
CLK Cycle Time
200
-
125
-
80
-
ns
(15)TDCL
CLK HIGH to READ or WRITE LOW
Delay
-
190
-
130
-
120
ns
(16)TDCTR
READ HIGH from CLK HIGH (S4)
Delay Time
-
190
-
115
-
80
ns
(17)TDCTW
WRITE HIGH from CLK HIGH (S4)
Delay Time
-
130
-
80
-
70
ns
(18)TDQ
HRQ Valid from CLK HIGH
Delay Time
-
120
-
75
-
30
ns
(19)TEPH
EOP Hold Time from CLK LOW (S2)
90
-
90
-
50
-
ns
(20)TEPS
EOP LOW to CLK LOW Setup Time
40
-
25
-
0
-
ns
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