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參數(shù)資料
| 型號(hào)： | 82C51A |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| 中文描述： | 通用同步異步收發(fā)器 |
| 文件頁數(shù)： | 18/26頁 |
| 文件大小： | 203K |
| 代理商： | 82C51A |
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Semiconductor
MSM82C51A-2RS/GS/JS
Receiver Control and Flag Timing (SYNC Mode)
x x x x x x 0 1 2 3 4
0 1 2 3 4
PAR
PAR
PAR
PAR
PAR
PAR
x x x x x x x
PAR
0 1 2 3 4
PAR
SYNDET
(Pin) (Note 1)
SYNDET (SB)
OVERRUN
ERROR (SB)
RXRDY (PIN)
C/
D
WR
RD
RXD
Don't
Care
SYNC
SYNC
Data
CHAR 1
Data
Data
CHAR 3
SYNC
SYNC
Don't Care
Data
Data
ETC
CHAR ASSY Begins
Exit Hunt Mode
Set SYNDET
Exit Hunt Mode
Set SYNDET (Status bit)
Set SYNDET (Status bit)
CHAR ASSY
Begins
Wr EH
RxEn
Rd Data
Rd Status
Wr Err Res
Rd Data
Rd SYNC
Rd Status
Rd Status
Data
t
IS
t
ES
(Note 2)
Note:
PAR
1. Internal Synchronization is based on the case of 5 data bit length + parity bit and 2 synchronous charactor.
2. External Synchronization is based on the case of 5 data bit length + parity bit.
Note:
1. Half-bit processing for the start bit
When the MSM82C51A-2 is used in the asynchronous mode, some problems are
caused in the processing for the start bit whose length is smaller than the 1-data bit
length. (See Fig. 1.)
2. Parity flag after a break signal is received (See Fig. 2.)
When the MSM82C51A-2 is used in the asynchrous mode, a parity flag may be set
when the next normal data is read after a break signal is received.
A parity flag is set when the rising edge of the break signal (end of the break signal)
is changed between the final data bit and the parity bit, through a RXRDY signal may
not be outputted.
If this occurs, the parity flag is left set when the next normal dats is received, and the
received data seems to be a parity error.
Smaller than 7-Receiver Clock Length
Smaller than 31-Receiver Clock Length
8-Receiver Clock Length
32-Receiver Clock Length
9 to 16-Receiver Clock Length
33 to 64-Receiver Clock Length
￥
16
￥
64
￥
16
￥
64
￥
16
￥
64
Start bit Length
Mode
Operation
The short start bit is ignored. (Normal)
The short start bit is ignored. (Normal)
Data cannot be received correctly due to a malfunction.
Data cannot be received correctly due to a malfunction.
The bit is regarded as a start bit. (normal)
The bit is regarded as a start bit. (normal)
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