參數(shù)資料
型號： 845GE
廠商： Intel Corp.
英文描述： 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述： 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH）
文件頁數(shù)： 77/176頁
文件大?。?/td> 2661K
代理商： 845GE
Intel
82845GE/82845PE Datasheet
77
Register Description
3.5.2.3
PCICMD1—PCI Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
04–05h
0000h
RO, R/W
16 bits
Bit
Description
15:10
Reserved.
9
Fast Back-to-Back Enable (FB2B)—RO.
Hardwired to 0.
8
SERR Message Enable (SERRE).
This bit is a global enable bit for Device 1 SERR messaging. The
(G)MCH communicates the SERR# condition by sending an SERR message to the ICH. If this bit is
set to a 1, the (G)MCH is enabled to generate SERR messages over HI for specific Device 1 error
conditions that are individually enabled in the BCTRL1 register. The error status is reported in the
PCISTS1 register. If SERRE1 is reset to 0, then the SERR message is not generated by the (G)MCH
for Device 1.
7
Address/Data Stepping (ADSTEP).
Hardwired to 0. Address/data stepping is not implemented in
the (G)MCH.
6
Parity Error Enable (PERRE).
Hardwired to 0. Parity checking is not supported on the primary side
of this device.
5
Reserved.
4
Memory Write and Invalidate Enable (MWIE).
Hardwired to 0.
3
Special Cycle Enable (SCE).
Hardwired to 0.
2
Bus Master Enable (BME).
0 = Disable (Default). AGP Master initiated Frame# cycles are ignored by the (G)MCH. The result is
a master abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI bridge
effectively disabled the bus master on the primary side.
1 = AGP master initiated Frame# cycles are accepted by the (G)MCH if they hit a valid address
decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles.
1
Memory Access Enable (MAE).
0 = Disable. All of Device 1’s memory space is disabled.
1 = Enable. This bit must be set to 1 to enable the Memory and Pre-fetchable memory address
ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
0
IO Access Enable (IOAE).
0 = Disable. All of Device 1’s I/O space is disabled.
1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and
IOLIMIT1 registers.
相關(guān)PDF資料
PDF描述
845PE 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
845G Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
845GL Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
845GV Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
8460 LAN 10/100 Base-TX Dual Port Transformer Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
845GE MAX-L 制造商:Micro-Star International 功能描述:845GE P4/CELERON 533FSB ATX - Bulk
845GEM-L 制造商:Micro-Star International 功能描述:845GEM-L P4 MATX HYPER-T - Bulk
845GL 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
845GLMS-L 制造商:Micro-Star International 功能描述:845GL UATX P4/CEL 400FSB - Bulk
845GR 制造商:SPC 功能描述:New
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