參數(shù)資料
型號: 85408BGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 85408 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝: 4.40 X 7.80 MM, 0.925 MM HEIGHT, MO-153, TSSOP-24
文件頁數(shù): 12/16頁
文件大?。?/td> 755K
代理商: 85408BGI
ICS85408I Datasheet
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
ICS85408BGI REVISION B JULY 2, 2009
5
2009 Integrated Device Technology, Inc.
Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crossing
point of the input to the differential output crossing point.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
Differential Output Voltage
RL = 100
250
400
600
mV
V
OD
VOD Magnitude Change
RL = 100
50
mV
VOS
Offset Voltage
RL = 100
1.125
1.4
1.6
V
OS
VOS Magnitude Change
RL = 100
50
mV
IOz
High Impedance Leakage
-10
+10
A
IOFF
Power Off Leakage
-1
+1
A
IOSD
Differential Output Short
Circuit Current
-5.5
mA
IOS/IOSB
Output Short Circuit Current
-12
mA
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
700
MHz
tPD
Propagation Delay; NOTE 1
1.6
2.4
ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
156.25MHz,
Integration Range: (12kHz – 20MHz)
167
fs
tsk(o)
Output Skew; NOTE 2, 4
50
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
550
ps
tR / tF
Output Rise/Fall Time
20% to 80%
50
600
ps
odc
Output Duty Cycle
45
55
%
tPZL, tPZH Output Enable Time; NOTE 5
5ns
tPLZ, tPHZ Output Disable Time; NOTE 5
5ns
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