參數(shù)資料
型號: 934033430118
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: 3.4 A, 30 V, 0.1 ohm, 2 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-012AA
封裝: PLASTIC, SMD, SO-8
文件頁數(shù): 1/7頁
文件大小: 94K
代理商: 934033430118
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM transistor
FEATURES
SYMBOL
QUICK REFERENCE DATA
Dual device
V
DS = 30 V
Low threshold voltage
Fast switching
I
D = 3.4 A
Logic level compatible
Surface mount package
R
DS(ON) ≤ 100 m (VGS = 10 V)
R
DS(ON) ≤ 200 m (VGS = 4.5 V)
GENERAL DESCRIPTION
PINNING
SOT96-1
Dual
N-channel
enhancement
PIN
DESCRIPTION
mode field-effect transistor in a
plastic envelope using ’trench
1
source 1
technology.
2
gate 1
Applications:-
Motor and relay drivers
3
source 2
d.c. to d.c. converters
Logic level translator
4
gate 2
The PHN210 is supplied in the
5,6
drain 2
SOT96-1 (SO8) surface mounting
package.
7,8
drain 1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Repetitive peak drain-source
T
j = 25 C to 150C
-
30
V
voltage
V
DS
Continuous drain-source voltage
-
30
V
DGR
Drain-gate voltage
R
GS = 20 k
-30
V
GS
Gate-source voltage
-
± 20
V
I
D
Drain current per MOSFET
1
T
a = 25 C
-
3.4
A
T
a = 70 C
-
2.8
A
I
D
Drain current per MOSFET (both
T
a = 25 C
-
2.4
A
MOSFETs conducting)
1
T
a = 70 C
-
1.9
A
I
DM
Drain current per MOSFET (pulse
T
a = 25 C
-
14
A
peak value)
P
tot
Total power dissipation (either or
T
a = 25 C
-
2
W
both MOSFETs conducting)
1
T
a = 70 C
-
1.3
W
T
stg, Tj
Storage & operating temperature
- 65
150
C
d1
g1
s1
d1
d2
g2
d2
s2
12
34
5
6
7
8
pin 1 index
1 Surface mounted on FR4 board, t
≤ 10 sec
January 2002
1
Rev 1.100
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