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參數(shù)資料
| 型號： | 935047940623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 935047940623 |
Philips Semiconductors
Product data
74ABT648
Octal bus transceiver/register, inverting (3-State)
2
2002 Dec 13
FEATURES
Combines 74ABT245 and 74ABT374 type functions in one device
Independent registers for A and B buses
Multiplexed real-time and stored data
Output capability: +64 mA / –32 mA
Power-up 3-state
Power-up reset
Live insertion/extraction permitted
Latch-up protection exceeds 500 mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT648 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT648 transceiver/register consists of bus transceiver
circuits with inverting 3-State outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from
the input bus or the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes HIGH.
Output Enable (OE) and DIR pins are provided to control the
transceiver function. In the transceiver mode, data present at the
high impedance port may be stored in either the A or B register or
both.
The Select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real-time. The DIR determines
which bus will receive data when the OE is active (LOW). In the
isolation mode (OE = HIGH), data from Bus A may be stored in the
B register and/or data from Bus B may be stored in the A register.
Outputs from real-time, or stored registers will be inverted. When an
output function is disabled, the input function is still enabled and
may be used to store and transmit data. Only one of the two buses,
A or B may be driven at a time. The examples on the next page
demonstrate the four fundamental bus management functions that
can be performed with the 74ABT648.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25 °C; GND = 0 V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50 pF; VCC = 5 V
5.9
ns
CIN
Input capacitance
CP, S, OE, DIR
VI = 0 V or VCC
4
pF
CI/O
I/O capacitance
Outputs disabled;
VO = 0 V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC =5.5 V
110
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
PART NUMBER
DWG NUMBER
24-Pin plastic SO
–40
°C to +85 °C
74ABT648D
SOT137-1
24-Pin Plastic TSSOP Type I
–40
°C to +85 °C
74ABT648PW
SOT355-1
PIN CONFIGURATION
SA00082
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
11
12
VCC
CPBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
13
14
15
16
17
18
19
20
21
22
23
24
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 23
CPAB /
CPBA
A to B clock input /
B to A clock input
2, 22
SAB /
SBA
A to B select input /
B to A select input
3
DIR
Direction control input
4, 5, 6, 7,
8, 9, 10, 11
A0 – A7
Data inputs/outputs (A side)
20, 19, 18, 17,
16, 15, 14, 13
B0 – B7
Data inputs/outputs (B side)
21
OE
Output enable input
(active-LOW)
12
GND
Ground (0 V)
24
VCC
Positive supply voltage
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