參數(shù)資料
型號(hào)： 935086530512
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 43/112頁(yè)
文件大?。?/td> 693K
代理商： 935086530512
1996 Jun 27
36
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xC592
Notes to the description of the CMR bits
1. The RX0/RX1 Active bits, if being read, reflect the status of the respective switches (see Fig.16). It is recommended
to change the switches only during the reset state (Reset Request = HIGH).
2. The Wake-Up Mode bit should be set at the same time as the Sleep bit. The differential wake up mode is useful if
both bus wires are fully functioning; it minimizes the amount of wake ups due to noise. The single ended wake up
mode is recommended if a wake up must be possible even if one bus wire is already or may become disturbed
(see Fig.16).
3. The CAN-controller will enter sleep mode, if the Sleep bit is set HIGH (sleep) there is no bus activity and no interrupt
is pending. The CAN-controller will wake up after the Sleep bit is set LOW (wake up) or when there is bus activity.
On wake up, a Wake-Up Interrupt (see Section 13.5.6) is generated (see also Chapter 15). A CAN-controller which
is sleeping and then awaken by bus activity will not be able to receive this message until it detects a Bus-Free signal
(see Section 13.6.9.6). The Sleep bit, if read, reflects the status of the CAN-controller.
4. This command bit is used to acknowledge the Data Overrun condition signalled by the Data Overrun status bit.
Command is given only after releasing both receive buffers. The stored messages have to be rejected. The
command bit is set simultaneously with setting of the Release Receive Buffer command bit the second time.
5. After reading the contents of the Receive Buffer (RBF0 or RBF1) the CPU must release this buffer by setting Release
Receive Buffer bit HIGH (released). This may result in another message becoming immediately available.
To prevent the RRB command being executed only once, the minimum wait time between two successive RRB
commands is 3 system clock cycles (tSCL, see Section 13.5.9).
6. The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission,
e.g. to transmit an urgent message. A transmission already in progress is not stopped. In order to see if the original
message had been either transmitted successfully or aborted, the Transmission Complete Status bit should be
checked. This should be done after the Transmit Buffer Access bit has been set HIGH (released) or a Transmit
Interrupt has been generated (see Section 13.5.6).
7. If the Transmission Request bit was set HIGH in a previous command, it cannot be cancelled by setting the
Transmission Request bit LOW (absent). Cancellation of the requested transmission may be performed by setting
the Abort Transmission bit HIGH (present).
Table 35 Combination of bits RX0A and RX1A (see Fig.16)
CONTROL
RX0
RX1
RX0A
RX1A
1
CRX0
CRX1
1
0
CRX0
1
2AVDD
01
1
2AVDD
CRX1
0
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