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| 型號： | 935086530512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 46/112頁 |
| 文件大小： | 693K |
| 代理商： | 935086530512 |
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1996 Jun 27
39
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xC592
13.5.6
INTERRUPT REGISTER (IR)
The Interrupt Register allows the identification of an interrupt source. When one or more bits of this register are set, a
CAN interrupt (SI01) will be indicated to the CPU. All bits are reset by the CAN-controller after this register is read by the
CPU. This register appears to the CPU as a read only memory.
Table 38 Interrupt Register (address 3)
Table 39 Description of the IR bits
Notes
1. Overrun Interrupt bit (if enabled) and Data Overrun bit (see Section 13.5.5) are set at the same time.
2. Receive Interrupt bit (if enabled) and Receive Buffer Status bit (see Section 13.5.5) are set at the same time.
76543210
WUI
OI
EI
TI
RI
BIT SYMBOL
FUNCTION
7
Reserved.
6
Reserved.
5
Reserved.
4
WUI
Wake-Up Interrupt. The value of WUI is set to:
HIGH (set), when the sleep mode is left. See Section 13.5.4.
LOW (reset), by a read access of the Interrupt Register by the CPU.
3OI
Overrun Interrupt (note 1). The value of OI is set to:
HIGH (set), if both Receive Buffers contain a message and the first byte of another message should
be stored (passed acceptance), and the Overrun Interrupt Enable is HIGH (enabled).
LOW (reset), by a read access of the Interrupt Register by the CPU.
2EI
Error Interrupt. The value of EI is set to:
HIGH (set), on a change of either the Error Status or Bus Status bits, if the Error Interrupt Enable is
HIGH (enabled). See Section 13.5.5.
LOW (reset), by a read access of the Interrupt Register by the CPU.
1TI
Transmit Interrupt. The value of TI is set to:
HIGH (set), on a change of the Transmit Buffer Access from LOW to HIGH (released) and
Transmit Interrupt Enable is HIGH (enabled).
LOW (reset), after a read access of the Interrupt Register by the CPU.
0RI
Receive Interrupt (note 2). The value of RBS is set to:
HIGH (set), when a new message is available in the Receive Buffer and the Receive Interrupt
Enable bit is HIGH (enabled).
LOW (reset) automatically by a read access of Interrupt Register by the CPU.
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