參數(shù)資料
型號(hào)： 935165760551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 X 2.70 MM, PLASTIC, QFP-80
文件頁(yè)數(shù)： 45/112頁(yè)
文件大?。?/td> 707K
代理商： 935165760551
1996 Jun 27
38
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.5
STATUS REGISTER (SR)
The contents of the Status Register reflects the status of the CAN-controller. The Status Register appears to the CPU
as a read only memory.
Table 36 Status Register (address 2)
Table 37 Description of the SR bits
76543210
BS
ES
TS
RS
TCS
TBS
DO
RBS
BIT
SYMBOL
FUNCTION
7BS
Bus Status (note 1). If the value of BS is:
HIGH (Bus-OFF), then the CAN-controller is not involved in bus activities.
LOW (Bus-ON), then the CAN-controller is involved in bus activities.
6ES
Error Status. If the value of ES is:
HIGH (error), then at least one of the Error Counters (see Section 13.6.10) has
reached the
CPU Warning limit.
LOW (ok), then both Error Counters have not reached the warning limit.
5TS
Transmit Status (note 2). If the value of TS is:
HIGH (transmit), then the CAN-controller is transmitting a message.
LOW (idle), then no message is transmitted.
4RS
Receive Status (note 2). If the value of RS is:
HIGH (receive), then the CAN-controller is receiving a message.
LOW (idle), then no message is received.
3
TCS
Transmission Complete Status (note 3). If the value of TCS is:
HIGH (complete), then last requested transmission has been successfully completed.
LOW (incomplete), then previously requested transmission is not yet completed.
2
TBS
Transmit Buffer Access (note 3). If the value of TBS is:
HIGH (released), then the CPU may write a message into the TBF.
LOW (locked), then the CPU cannot access the Transmit Buffer. A message is either
waiting for transmission or is in the process of being transmitted.
1DO
Data Overrun (note 4). If the value of DO is:
HIGH (overrun), then both Receive Buffers are full and the first byte of another
message should be stored.
LOW (absent), then no data overrun has occurred since the Clear Overrun command
was given.
0
RBS
Receive Buffer Status (note 5). If the value of RBS is:
HIGH (full), then this bit is set when a new message is available.
LOW (empty), then no message has become available since the last Release Receive
Buffer command bit was set.
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