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參數(shù)資料
| 型號： | 935165760551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 81/112頁 |
| 文件大?。?/td> | 707K |
| 代理商： | 935165760551 |
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1996 Jun 27
70
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
15.4
Power-down Mode
The instruction that sets bit PCON.1 to HIGH, is the last
one executed before entering the Power-down mode. In
Power-down mode the oscillator of the P8xCE598 is
stopped. If the CAN Controller is in use, it is recommended
to set it into Sleep mode before entering Power-down
mode. However, setting PCON.1 to HIGH also sets the
Sleep bit (CAN Controller Command Register bit 4) to
HIGH.
The P8xCE598 leaves Power-down mode either by a
hardware reset or by a CAN Wake-Up interrupt
(due to activity on the CAN-bus),
if the SIO1 (CAN) interrupt source is enabled
(contents of register IEN0 = 1X1XXXXXB).
A hardware reset affects the whole P8xCE598, but leaves
the contents of the on-chip RAM unchanged
(CAN Controller-and CPU's SFRs are reset, see
Section 13.5.2, Chapter 17 and Table 40). A CAN
Wake-Up interrupt during Power-down mode causes a
reset output pulse with a width of 6144 machine cycles
(4.6 ms with fCLK = 16 MHz). All hardware except that for
the CAN Controller of the P8xCE598 is reset (i.e. the
contents of all CAN Controller registers are preserved).
A capacitance connected to the RST pin can be used to
lengthen the internally generated reset pulse. If the pulse
exceeds 8192 machine cycles, the CAN Controller part is
reset too.
Table 82 Status of external pins during Idle and Power-down modes
Note
1. If the port pins P1.6 and P1.7 are used as the CAN transmitter outputs (CTX0 and CTX1), then during Sleep and
Power-down mode these pins output a ‘recessive’ level (see Sections 13.5.2 and 13.5.11).
MODE
PROGRAM
ALE
PSEN
PORT0
PORT1(1)
PORT2
PORT3
PORT4
PWM0/
PWM1
Idle
internal
1
port data
1
external
1
oating
port data
address
port data
1
Power-down
internal
0
port data
1
external
0
oating
port data
1
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