參數(shù)資料
型號： 935165760551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 X 2.70 MM, PLASTIC, QFP-80
文件頁數(shù)： 79/112頁
文件大小： 707K
代理商： 935165760551
1996 Jun 27
69
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
15.1
Power Control Register (PCON)
Table 80 Power Control Register (address 87H)
Table 81 Description of the PCON bits
Note
1. If PD and IDL are set to HIGH at the same time, PD takes precedence. The reset value of PCON is 0X000000B.
76543210
SMOD
RFI
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
FUNCTION
7
SMOD
Double Baud rate bit. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in Modes 1, 2 and 3.
6
Reserved.
5
RFI
RFI-Reduction Mode bit. When set to HIGH the toggling of ALE pin is prohibited. This
bit is cleared on RESET; see also ALE/PROG in Sections 2.1 and 2.2.
4
WLE
Watchdog Load Enable. This ag must be set by software prior to loading T3
(watchdog timer). It is cleared when T3 is loaded.
3
GF1
General purpose ag bits.
2
GF0
1PD
Power-down bit. Setting this bit activates Power-down mode (note 1). It can only be set
if input EW is HIGH.
0
IDL
Idle mode bit. Setting this bit activates the Idle mode (note 1).
15.2
CAN Sleep Mode
In order to reduce power consumption of the P8xCE598
the CAN Controller may be switched off (disconnecting the
internal clock) by setting the CAN Command Register bit 4
(Sleep) HIGH. The CAN Controller leaves this Sleep mode
by detecting either activity on the CAN-bus (dominant
bit-level on CRX0/CRX1; see Chapter 5, Table 1) or by
setting the Sleep bit to LOW. As the CPU can not only write
to the Sleep bit, but can also read it, the CAN Controller
status can be determined directly.
15.3
Idle Mode
The instruction that sets bit PCON.0 to HIGH is the last
one executed in the normal operating mode before Idle
mode is activated.
Once in the Idle mode, the CPU status is preserved in its
entirety: the Stack Pointer, Program Counter, Program
Status Word, Accumulator, RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in see Table 82.
There are three ways to terminate the Idle mode:
Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware, provided that the interrupt
source is active during Idle mode. After the interrupt is
serviced, the program continues with the instruction
immediately after the one, at which the interrupt request
was detected.
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by
an interrupt, the service routine can examine the status
of the flag bits.
Another way of terminating the Idle mode is an external
hardware reset. Since the oscillator is still running, the
reset signal is required to be active only for two machine
cycles (24 oscillator periods) to complete to reset
operation.
The third way is the internally generated watchdog reset
after an overflow of Timer 3.
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