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參數(shù)資料
| 型號： | 935189960118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP-16 |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935189960118 |
11
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend-
ing interrupts, as shown in the following example.
Note:
4.7.1
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe-
cution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the
selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program
Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG
is set.
4.8
Register Description
4.8.1
CCP – Configuration Change Protection Register
Bits 7:0 – CCP[7:0] – Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct
signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction
cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again
by the CPU, and any pending interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is
enabled, while CCP[7:1] will always read as zero.
Table 4-1 shows the signatures that are in recognised.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
Bit
7
6
5432
10
CCP[7:0]
CCP
Read/Write
W
WWWW
WW
R/W
Initial Value
0
0000
00
Table 4-1.
Signatures Recognised by the Configuration Change Protection Register
Signature
Group
Description
0xD8
IOREG: CLKMSR, CLKPSR, WDTCSR
Protected I/O register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 933715220112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189070118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 935189960112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189350112 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933715220118 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
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