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參數(shù)資料
| 型號： | 935189960118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP-16 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935189960118 |
12
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
4.8.2
SPH and SPL — Stack Pointer Register
4.8.3
SREG – Status Register
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the inter-
rupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the document “AVR Instruction
Set” and “Instruction Set Summary” on page 150.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the oper-
ated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information.
Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See document “AVR Instruction
Set” and section “Instruction Set Summary” on page 150 for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See document “AVR Instruction
Set” and section “Instruction Set Summary” on page 150 for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR Instruction Set” and
section “Instruction Set Summary” on page 150 for detailed information.
Bit
151413121110
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
765
43210
Read/Write
R/W
Read/Write
R/W
Initial Value
RAMEND
Initial Value
RAMEND
Bit
7
6
5432
10
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
Initial Value
0
0000
00
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 933715220112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189070118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 935189960112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189350112 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933715220118 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
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