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參數(shù)資料
| 型號： | 935243450557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 261K |
| 代理商： | 935243450557 |
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1997 Jan 06
18
Philips Semiconductors
Preliminary specication
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
Table 22 Subaddress 63 to 66 (four bytes to program subcarrier frequency)
Note
1. Examples:
a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH).
b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH).
Table 23 Subaddress 67 to 6A
Table 24 Subaddress 6B
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
FSC0 to FSC3
ffsc = subcarrier frequency (in
multiples of line frequency);
fllc = clock frequency (in multiples
of line frequency)
,
rounded up; see note 1
FSC3 = most signicant byte
FSC0 = least signicant byte
DATA BYTE
DESCRIPTION
REMARKS
L21O0
rst byte of captioning data, odd eld
LSBs of the respective bytes are encoded
immediately after run-in and framing code, the
MSBs of the respective bytes have to carry the
parity bit, in accordance with the denition of
Line 21 encoding format.
L21O1
second byte of captioning data, odd eld
L21E0
rst byte of extended data, even eld
L21E1
second byte of extended data, even eld
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
PRCV2
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively
ORCV2
0
pin RCV2 is switched to input; default after reset
1
pin RCV2 is switched to output
CBLF
0
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse that is
dened by RCV2S and RCV2E, also during vertical blanking Interval); default after reset
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, for example a
reference pulse that is dened by RCV2S and RCV2E, excluding Vertical Blanking Interval,
which is dened by FAL and LAL
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal
PRCV1
0
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset
1
polarity of RCV1 as output is active LOW, falling edge is taken when input
ORCV1
0
pin RCV1 is switched to input; default after reset
1
pin RCV1 is switched to output
TRCV2
0
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset
1
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
SRCV1
denes signal type on pin RCV1; see Table 25
FSC
f
fsc
f
llc
--------
2
32
×
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