1997 Jan 06
26
Philips Semiconductors
Preliminary specication
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
Fig.10 RTCI timing.
handbook, full pagewidth
128
13
14
19
67
69 72 74
68
01
0
21
RTCI
HPLL
increment
FSCPLL increment (1)
H/L transition
count start
4 bits
reserved (7)
valid
sample
invalid
sample
not used in SAA7120/21
5 bits
reserved (7)
8/LLC
MBH789
LOW
time slot:
(2)
(3)
(5)
(6)
(4)
(3) Reset bit: only from SAA7111 decoder.
(4) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(5) Odd/even bit: odd/even from external.
(6) Colour detection: 0 = no colour detected, 1 = colour detected.
(7) Reserved bits: 232 with 50 Hz systems, 229 with 60 Hz systems.
(1) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before
sequence bit.
(2) Sequence bit
PAL: 0 = (R
Y) line normal, 1 = (RY) line inverted
NTSC: 0 = no change.
Explanation of RTCI data bits
1. The ConDENC generates the subcarrier frequency out
of the FSCPLL increment if enabled (see item 6.).
2. The PAL bit indicates the line with inverted R - Y
component of colour difference signal.
3. If the reset bit is enabled
(RTCE = 1; DECPH = 1; PHRES = 00), the phase of
the subcarrier is reset in each line whenever the reset
bit of RTCI input is set to 1.
4. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the
ConDENC takes this bit instead of the FISE bit in
subaddress 61H.
5. If the odd/even bit is enabled (RTCE = 1; DECOE = 1),
the ConDENC ignores its internally generated
odd/even flag and takes the odd/even bit from RTCI
input.
6. If the colour detection bit is enabled (RTCE = 1;
DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the ConDENC. In the other case (colour
detection bit = 1) the subcarrier frequency is evaluated
out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.