1997 Jan 06
21
Philips Semiconductors
Preliminary specication
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
Table 34 Subaddress 73 and 74
Table 35 Subaddress 75
Table 36 Subaddress 76, 77 and 7C
Table 37 Subaddress 78, 79 and 7C
Table 38 Subaddress 7C
Table 39 Subaddress 7A to 7C
DATA BYTE
DESCRIPTION
TTXHS
start of signal on pin TTXRQ see Fig.7
TTXHD
indicates the delay in clock cycles between rising edge of TTXRQ output and valid data on pin TTX
minimum value has to be TTXHD = 2
DATA BYTE
DESCRIPTION
VS_S
Vertical Sync. shift between RCV1 and RCV2 (switched to output) in master mode it is possible to shift
H-sync (RCV2; CBLF = 0) against V-sync (RCV1; SRCV1 = 00)
standard value: VS_S = 3
DATA BYTE
DESCRIPTION
TTXOVS
rst line of occurrence of signal on pin TTXRQ in odd eld
line = (TTXOVS + 4) for M-systems
line = (TTXOVS + 1) for other systems
TTXOVE
last line of occurrence of signal on pin TTXRQ in odd eld
line = (TTXOVE + 3) for M-systems
line = TTXOVE for other systems
DATA BYTE
DESCRIPTION
TTXEVS
rst line of occurrence of signal on pin TTXRQ in even eld
line = (TTXEVS + 4) for M-systems
line = (TTXEVS + 1) for other systems
TTXEVE
last line of occurrence of signal on pin TTXRQ in even eld
line = (TTXEVE + 3) for M-systems
line = TTXEVE for other systems
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
TTX60
0
enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset
1
enables World Standard Teletext 60 Hz (FISE = 1)
DATA BYTE
DESCRIPTION
FAL
rst active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0
coincides with the rst eld synchronization pulse
LAL
last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides
with the rst eld synchronization pulse