參數(shù)資料
型號(hào): 935246150005
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
封裝: CHIP ON WAFER
文件頁(yè)數(shù): 2/68頁(yè)
文件大?。?/td> 234K
代理商: 935246150005
2000 Jan 04
10
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
6.3.2
RESET VALUES
Detection of a ‘reset request’ results in aborting the current transmission/reception of a message and entering the reset
mode. On the ‘1-to-0’ transition of the reset request bit, the CAN controller returns to the operating mode.
Table 2
Reset mode conguration; notes 1 and 2
REGISTER
BIT
SYMBOL
NAME
VALUE
RESET BY
HARDWARE
SETTING
BIT CR.0 BY
SOFTWARE OR
DUE TO
BUS-OFF
Control
CR.7
reserved
0
CR.6
reserved
X
CR.5
reserved
1
CR.4
OIE
Overrun Interrupt Enable
X
CR.3
EIE
Error Interrupt Enable
X
CR.2
TIE
Transmit Interrupt Enable
X
CR.1
RIE
Receive Interrupt Enable
X
CR.0
RR
Reset Request
1 (reset mode)
Command
CMR.7
reserved
note 3
CMR.6
reserved
CMR.5
reserved
CMR.4
GTS
Go To Sleep
CMR.3
CDO
Clear Data Overrun
CMR.2
RRB
Release Receive Buffer
CMR.1
AT
Abort Transmission
CMR.0
TR
Transmission Request
Status
SR.7
BS
Bus Status
0 (bus-on)
X
SR.6
ES
Error Status
0 (ok)
X
SR.5
TS
Transmit Status
0 (idle)
SR.4
RS
Receive Status
0 (idle)
SR.3
TCS
Transmission Complete Status
1 (complete)
X
SR.2
TBS
Transmit Buffer Status
1 (released)
SR.1
DOS
Data Overrun Status
0 (absent)
SR.0
RBS
Receive Buffer Status
0 (empty)
Interrupt
IR.7
reserved
1
IR.6
reserved
1
IR.5
reserved
1
IR.4
WUI
Wake-Up Interrupt
0 (reset)
IR.3
DOI
Data Overrun Interrupt
0 (reset)
IR.2
EI
Error Interrupt
0 (reset)
X; note 4
IR.1
TI
Transmit Interrupt
0 (reset)
IR.0
RI
Receive Interrupt
0 (reset)
相關(guān)PDF資料
PDF描述
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
08NU08NU INNENGEWINDE BSP DREHB G 0.5
08NU10NU INNENGEWINDE BSP DREHB G 0.5X0.63ZOLL
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