參數(shù)資料
型號： 935246150005
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
封裝： CHIP ON WAFER
文件頁數(shù)： 5/68頁
文件大?。?/td> 234K
代理商： 935246150005
2000 Jan 04
13
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Notes
1. Any write access to the control register has to set this bit to logic 0 (reset value is logic 0).
2. In the PCA82C200 this bit was used to select the synchronization mode. Because this mode is not longer
implemented, setting this bit has no influence on the microcontroller. Due to software compatibility setting this bit is
allowed. This bit will not change after hardware or software reset. In addition the value written by users software is
reflected.
3. Reading this bit will always reflect a logic 1.
4. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset request bit is set to logic 1
(present). If this bit is accessed by software, a value change will become visible and takes effect first with the next
positive edge of the internal clock which operates with 1
2 of the external oscillator frequency. During an external reset
the microcontroller cannot set the reset request bit to logic 0 (absent). Therefore, after having set the reset request
bit to logic 0, the microcontroller must check this bit to ensure that the external reset pin is not being held LOW.
Changes of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit
reflects the synchronized status.
After the reset request bit is set to logic 0 the SJA1000 will wait for:
a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset request has been caused by a
hardware reset or a CPU-initiated reset
b) 128 occurrences of bus-free, if the preceding reset request has been caused by a CAN controller initiated bus-off,
before re-entering the bus-on mode; it should be noted that several registers are modified if the reset request bit
was set (see also Table 2).
6.3.4
COMMAND REGISTER (CMR)
A command bit initiates an action within the transfer layer of the SJA1000. The command register appears to the
microcontroller as a write only memory. If a read access is performed to this address the byte ‘11111111’ is returned.
Between two commands at least one internal clock cycle is needed to process. The internal clock is divided by two from
the external oscillator frequency.
CR.1
RIE
Receive Interrupt Enable
1
enabled; when a message has been received
without errors, the SJA1000 transmits a receive
interrupt signal to the microcontroller
0
disabled; the microcontroller receives no transmit
interrupt signal from the SJA1000
CR.0
RR
Reset Request; note 4
1
present; detection of a reset request results in
aborting the current transmission/reception of a
message and entering the reset mode
0
absent; on the ‘1-to-0’ transition of the reset
request bit, the SJA1000 returns to the operating
mode
BIT
SYMBOL
NAME
VALUE
FUNCTION
相關(guān)PDF資料
PDF描述
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
08NU08NU INNENGEWINDE BSP DREHB G 0.5
08NU10NU INNENGEWINDE BSP DREHB G 0.5X0.63ZOLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
935248-90 制造商:JANCO 功能描述:935248-90
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935252-5 制造商:C-H 功能描述:935252-5
935257650112 制造商:NXP Semiconductors 功能描述:SUB ONLY ICSUBS TO 935257650112
935260093112 制造商:NXP Semiconductors 功能描述:IC AVIC ADV BASESTATION 14SOIC
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