參數(shù)資料
型號： 935247890557
廠商： NXP SEMICONDUCTORS
元件分類： 畫面疊加
英文描述： PICTURE-IN-PICTURE IC, PQFP100
封裝： PLASTIC, SOT-317-2, QFP-100
文件頁數(shù)： 30/35頁
文件大?。?/td> 228K
代理商： 935247890557
1996 Aug 07
4
Philips Semiconductors
Preliminary specication
Picture-In-Picture (PIP) controller
SAB9077H
BLOCK DIAGRAM
ndbook, full pagewidth
MBH502
SY
SU
SV
SAV
bias
MAV
DDD
MAV
SSD
MAV
DDA
MAV
SSA
SAV
refT
SAV
refB
71
3
4
12
11
DAV
DDD
DAV
SSD
DAV
DDA
DAV
SSA
TACLK
TC
TDCLK
TM2
TM1
TM0
A0
SCL
SDA
POR
MCV
DDD
MCV
SSD
DCV
SSD
DCV
DDD
DV
DDD
DV
SSD
V
SSD
V
DDD
SCV
SSD
SCV
DDD
SPV
DDA
SPV
SSA
DPV
SSA
DPV
DDA
MPV
DDA
MPV
SSA
91
92
84
83
100
63
18
19
22
21
20
15
16
59
60
61
62
82
81
41
42
43
44
45
46
65
66
97
98
99
SAV
DDD
SAV
SSD
SAV
DDA
SAV
SSA
78
77
69
70
SV
DDD
SV
SSD
MV
DDD
MV
SSD
68
67
13
14
CAS
RAS
49
48
DAO0
to
DAO7
47
31
40
32,
34,
36,
38,
39,
37,
35,
33
DAI0
to
DAI7
23,
25,
27,
29,
30,
28,
26,
24
AD0
to
AD8
51,
53,
55,
57,
58,
56,
54,
52,
50
75
73
76
74
72
DY
DU
DV
DAV
bias
DAV
refT
DAV
refB
86
90
88
85
87
89
DFB
93
DT
WE
SC
DAC
AND
BUFFER
CLAMP
AND
ADC
MY
MU
MV
MAV
bias
MAV
refT
MAV
refB
10
6
8
5
7
9
CLAMP
AND
ADC
SPH
sync
SV
sync
SPV
bias
79
64
80
PLL
AND
CLOCK
GENERATOR
HORIZONTAL
AND
VERTICAL
FILTER
HORIZONTAL
AND
VERTICAL
FILTER
MPH
sync
MV
sync
MPV
bias
2
17
1
PLL
AND
CLOCK
GENERATOR
DPH
sync
DV
sync
DPV
bias
96
94
95
PLL
AND
CLOCK
GENERATOR
LINE
MEMORY
VDRAM
CONTROL
AND
(RE-)
FORMATTING
DISPLAY
CONTROL
LINE
MEMORY
I2
C-BUS
CONTROL
LINE
MEMORY
SAB9077H
Fig.1
Block
diagram.
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