參數(shù)資料
型號(hào)： 935247890557
廠商： NXP SEMICONDUCTORS
元件分類： 畫面疊加
英文描述： PICTURE-IN-PICTURE IC, PQFP100
封裝： PLASTIC, SOT-317-2, QFP-100
文件頁(yè)數(shù)： 8/35頁(yè)
文件大?。?/td> 228K
代理商： 935247890557
1996 Aug 07
16
Philips Semiconductors
Preliminary specication
Picture-In-Picture (PIP) controller
SAB9077H
SA 00H PIP REGISTER
MPIPON and SPIPON bits switch respectively the main
and sub PIPs of the SAB9077H on or off. The MFREEZE
and SFREEZE bits make the current live pictures for the
Main and Sub frozen. The writing to the VDRAM is
stopped.
The MCOPY bit copies the Main data direct to the output.
This mode should only be set when MREDV is 1/1. Table 2
gives more information when to set this bit. The PIPMODE
bits set the PIP mode in accordance with Table 3.
SA 01H DISPLAY REGISTER
M1FLD and S1FLD(1) bits control the use of the reserved
second field in the VDRAM. If this bit is set to logic 0 then
address spaces are reserved for both fields in the VDRAM.
This avoids joint line errors. Whether these address
spaces are used is dependent on the interlacing of the
input signals and the NONINT bits. If a 1FLD bit is set to
logic 1 then only 1 address space is used in the VDRAM
for both fields. In some PIP modes the use of a second
field is not possible since there is not enough space in the
VDRAM, in these modes the 1FLD bit must be set to
logic 1. The DNONINT bit controls the interlace mode of
the display part. If set to logic 1 then data is only read from
one field in the VDRAM. If set to logic 0 then both fields (if
available) are used for display.
MNONINT and SNONINT bits control the interlace mode
of the acquisition blocks. If set to logic 1 then data is only
written to one field in the VDRAM (two fields remain
allocated). If set to logic 0 then both fields (if available) are
used for acquisition.
The NIPCOFF bit determines whether a grey bar is
inserted in case a NTSC PIP is displayed in a PIP with PAL
PIP size. The missing lines are equally divided between
the top part and the bottom part of the PIP window and
made 30% grey. If this bit is set to logic 0 the grey bar is
displayed, if this bit is set to logic 1 the grey bar is omitted
and the PIP data is shifted up.
SA 02H DISPLAY REGISTER
The DFILT bit controls an interpolating filter that changes
the internal 864 pixels data rate to the output data rate of
2
× 864 pixels. If DFILT is set to logic 1 then the filter is on.
The FILLOFF bit controls filling of PIPs when the PIP mode
is switched. If FILLOFF is set to logic 0 then all PIPs are
filled with a 30% gray until their channel has been updated.
(1) If the 1 FLD bits are set to logic 1 the NONINT bits of the
corresponding channel must also be set to logic 1.
If FILLOFF is set to logic 1 then the VDRAM content is
always visible. This is useful when a new, ‘similar’ to the
previous one, PIP mode is set. The previous data can then
be displayed.
The SMART6 and SKIP6 bits control the data transfer
mode to the external VDRAM. For modes which display a
complete line (672 pixels) a form of data reduction has to
be carried out.
Two transfer modes are available. One is simply skipping
the 8-bit data path to 6-bit (SKIP6). The other is carry out
an intelligent data reduction which keeps an 8-bit
resolution (SMART6).
The YTH bits control the video output. If the current
Y-value is less then YTH
× 16 then the fast blank is
switched off, the original live background will be visible.
This feature can be used to pick up sub-titles and display
them as On-Screen Display (OSD) anywhere on the
screen.
SA 03H DISPLAY BACKGROUND FINE POSITIONING REGISTER
The BGHFP bits control the horizontal display positioning
of the background. The resolution is 16 steps of 4 pixels.
The BGVFP bits control the vertical display positioning of
the background. The resolution is 16 steps of 2 lines/field.
The background fine positioning moves the complete
display. It is a general offset of all the PIP pictures and
background, It is only meant to adjust once the centring of
all PIP modes (see Fig.3).
SA 04H AND SA 05H DISPLAY SUB-CHANNEL FINE
POSITIONING REGISTERS
These registers control the horizontal and vertical fine
positioning of the display sub-channel with respect to the
display background. This is the actual fine positioning (see
Fig.3). The horizontal resolution is 256 steps of 4 pixels
and the vertical resolution is 256 steps of 1 line/field.
SA 06H AND SA 07H DISPLAY MAIN-CHANNEL FINE
POSITIONING REGISTERS
These registers control the horizontal and vertical fine
positioning of the display main-channel with respect to the
display background. This is the actual fine positioning (see
Fig.3). The horizontal resolution is 256 steps of 4 pixels
and the vertical resolution is 256 steps of 1 line/field.
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