參數(shù)資料
型號(hào)： 935260017557
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, SOT-314, LQFP-64
文件頁數(shù)： 27/75頁
文件大?。?/td> 479K
代理商： 935260017557
1998 May 15
33
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
Fig.25 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0.
(2) Line numbers in parenthesis refer to CCIR line counting.
(3) Additional VREF positions can be achieved via I2C-bus bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
handbook, full pagewidth
VS
(266)
(267)
(268)
(269)
(270)
(271)
(272)
(273)
(274)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(20)
(3)
HREF
(b) 2nd field
(a) 1st field
input CVBS
(2)
(1)
(525)
(21)
(22)
(283)
(284)
(265)
(264)
(263)
(262)
VRLN = 1(3)
VRLN = 0(3)
VRLN = 1(3)
VRLN = 0(3)
1
2
34
567
8
17
525
524
523
522
18
19
263
264
265
266
267
268
269
270
271
280
281
262
261
260
259
(285)
282
(2)
MGG070
520 x 2/LLC
RTS0 (ODD)(1)
81 x 2/LLC
VREF
VS
HREF
input CVBS
RTS0 (ODD)(1)
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