參數(shù)資料
型號: 935260017557
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: PLASTIC, SOT-314, LQFP-64
文件頁數(shù): 42/75頁
文件大?。?/td> 479K
代理商: 935260017557
1998 May 15
47
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.7
SUBADDRESS 07
Table 19 Horizontal sync stop SA 07, D7 to D0
17.2.8
SUBADDRESS 08
Table 20 Sync control SA 08, D7 to D5, D3 to D0
DELAY TIME
(STEP SIZE = 8/LLC)
CONTROL BITS D7 to D0
HSS7
HSS6
HSS5
HSS4
HSS3
HSS2
HSS1
HSS0
128...108
forbidden (outside available central counter range)
107...
1
0
1
0
1
0
1
...108 (50Hz)
0
1
0
1
0
...107 (60Hz)
0
1
0
1
0
1
109...127 (50Hz)
forbidden (outside available central counter range)
108...127 (60Hz)
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Vertical noise reduction (VNOI)
Normal mode
VNOI1
0
D1
VNOI0
0
D0
Searching mode
VNOI1
0
D1
VNOI0
1
D0
Free running mode
VNOI1
1
D1
VNOI0
0
D0
Vertical noise reduction bypassed
VNOI1
1
D1
VNOI0
1
D0
Horizontal PLL (HPLL)
PLL closed
HPLL
0
D2
PLL open, horizontal frequency xed
HPLL
1
D2
TV/VTR mode select (VTRC)
TV mode
(recommended for poor quality TV signals only)
VTRC
0
D3
VTR mode (recommended as default setting)
VTRC
1
D3
Extended loop lter (EXFIL)
Word width of the loop lter (LF2) amplication = 16-bit
EXFIL
0
D5
Word width of the loop lter (LF2) amplication = 14-bit
EXFIL
1
D5
Field selection (FSEL)
50 Hz, 625 lines
FSEL
0
D6
60 Hz, 525 lines
FSEL
1
D6
Automatic eld detection (AUFD)
Field state directly controlled via FSEL
AUFD
0
D7
Automatic eld detection
AUFD
1
D7
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