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參數(shù)資料
| 型號： | 935260734118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 99K |
| 代理商： | 935260734118 |
2002 Jun 18
3
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset; positive-edge
trigger
74LVC74A
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC74AD
40 to +125 °C
14
SO
plastic
SOT108-1
74LVC74ADB
40 to +125 °C
14
SSOP
plastic
SOT337-1
74LVC74APW
40 to +125 °C
14
TSSOP
plastic
SOT402-1
FUNCTION TABLES
Table 1
See note 1.
Table 2
See note 1.
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP
transition.
PINNING
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQ
LH
X
HL
X
LH
LL
X
H
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQn+1
HH
↑
LL
H
HH
↑
HH
L
PIN
SYMBOL
DESCRIPTION
11RD
asynchronous reset-direct input
(active LOW)
2
1D
data inputs
3
1CP
clock input (LOW-to-HIGH,
edge-triggered)
41SD
asynchronous set-direct input
(active LOW)
5
1Q
true ip-op outputs
61Q
complement ip-op outputs
7
GND
ground (0 V)
82Q
complement ip-op outputs
9
2Q
true ip-op outputs
10
2SD
asynchronous set-direct input
(active LOW)
11
2CP
clock input (LOW-to-HIGH,
edge-triggered)
12
2D
data inputs
13
2RD
asynchronous reset-direct input
(active LOW)
14
VCC
supply voltage
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