參數(shù)資料
型號(hào)： 935260734118
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 鎖存器
英文描述： LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14
文件頁(yè)數(shù)： 17/20頁(yè)
文件大小： 99K
代理商： 935260734118
2002 Jun 18
6
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset; positive-edge
trigger
74LVC74A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
for maximum speed performance
2.7
3.6
V
for low-voltage applications
1.2
3.6
V
VI
input voltage
0
5.5
V
VO
output voltage
0
VCC
V
Tamb
ambient temperature
40
+125
°C
tr,tf
input rise and fall times
VCC = 1.2 to 2.7 V
0
20
ns/V
VCC = 2.7 to 3.6 V
0
10
ns/V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
0.5
+6.5
V
IIK
input diode current
VI <0
50
mA
VI
input voltage
note 1
0.5
+6.5
V
IOK
output diode current
VO >VCC or VO <0
±50
mA
VO
output voltage
note 1
0.5
VCC + 0.5 V
IO
output source or sink current
VO =0toVCC
±50
mA
IGND, ICC
VCC or GND current
±100
mA
Tstg
storage temperature
65
+150
°C
Ptot
power dissipation per package
SO
above 70
°C derate linearly with
8 mW/K
500
mW
SSOP and TSSOP
above 60
°C derate linearly with
5.5 mW/K
500
mW
相關(guān)PDF資料
PDF描述
935260742118 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
935260740112 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
935260741118 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
935260740118 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
935260742112 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
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