- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36337 > 935261504557 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP44 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935261504557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁(yè)數(shù)： | 39/87頁(yè) |
| 文件大?。?/td> | 440K |
| 代理商： | 935261504557 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)當(dāng)前第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)
1999 Jul 01
44
Philips Semiconductors
Product specication
9-bit video input processor
SAA7113H
Fig.30 Vertical timing diagram for 60 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR
or fast mode (HTC = 01 or 11)].
HREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H.
ODD: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH.
VS: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to 00 and/or RTSE13 to RTSE10 = BH.
V123: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH.
VREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH.
FID: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH.
(1) Line numbers in parenthesis refer to ITU line counting.
(2) VREF range short or long can be programmed via I2C-bus bit VRLN.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
(3) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52.
(4) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the
field is odd. If HREF is inactive during the falling edge of V123, the field is even. The specific position of the slope is dependent on the internal
processing delay and may change a few clock cycles from version to version.
handbook, full pagewidth
RTS0/1 VS
VRLN = 1(2)
(b) 2nd field
(a) 1st field
input CVBS
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(20)
(3)
(2)
(1)
(525)
(21)
(22)(1)
VRLN = 1(3) (2)
VRLN = 0(3) (2)
1
2
34
56
7
8
17
525
524
523
522
18
19
(266)
(267)
(268)
(269)
(270)
(271)
(272)
(273)
(274)
(283)
(284)
(265)
(264)
(263)
(262)
263
264
265
266
267
268
269
270
271
280
281
262
261
260
259
(285)(1)
282
MHB337
520
× 2/LLC
RTS0/1 ODD
81
× 2/LLC
VRLN = 0(2)
RST0/1 HREF
RTS0/1 VREF
RTS0/1 VS
RTS0/1 HREF
input CVBS
RTS0/1 ODD
RTS0/1 V123(4)
RTS0/1 FID(3)
RTS0/1 V123(4)
RTS0/1 FID(3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935261537118 | DELTA-SIGMA ADC, PDSO16 |
| 935261537112 | DELTA-SIGMA ADC, PDSO16 |
| 935261615112 | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 935261615118 | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 935261616112 | SPECIALTY CONSUMER CIRCUIT, PDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935262025112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935262217118 | 制造商:NXP Semiconductors 功能描述:Real Time Clock Serial 8-Pin SO T/R |
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。