參數(shù)資料
型號： 935261504557
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： PLASTIC, SOT-307, QFP-44
文件頁數(shù)： 56/87頁
文件大小： 440K
代理商： 935261504557
1999 Jul 01
6
Philips Semiconductors
Product specication
9-bit video input processor
SAA7113H
7
PINNING
SYMBOL
PIN
I/O/P
DESCRIPTION
AI22
1
I
analog input 22
VSSA1
2
P
ground for analog supply voltage channel 1
VDDA1
3
P
positive supply voltage for analog channel 1 (+3.3 V)
AI11
4
I
analog input 11
AI1D
5
I
differential analog input for AI11 and AI12; has to be connected to ground via a
capacitor; see application diagram of Fig.31
AGND
6
P
analog signal ground connection
AI12
7
I
analog input 12
TRST
8
I
test reset input (active LOW), for boundary scan test; notes 1, 2 and 3
AOUT
9
O
analog test output; for testing the analog input channels, 75
termination possible
VDDA0
10
P
positive supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC)
VSSA0
11
P
ground for internal clock generation circuit
VPO7 to
VPO4
12 to 15
O
digital VPO-bus output signal; higher bits of the 8-bit output bus. The output data
types of the VPO-bus are controlled via I2C-bus registers LCR2 to LCR24;
see Table 4. If I2C-bus bit VIPB = 1, the higher bits of the digitized input signal are
connected to these outputs, congured by the I2C-bus control signals
MODE3 to MODE0
VSSDE1
16
P
ground 1 or digital supply voltage input E (external pad supply)
LLC
17
O
line-locked system clock output (27 MHz)
VDDDE1
18
P
digital supply voltage E1 (external pad supply 1; +3.3 V)
VPO3 to
VPO0
19 to 22
O
digital VPO-bus output signal; lower bits of the 8-bit output bus. The output data types
of the VPO-bus are controlled via I2C-bus registers LCR2 to LCR24; see Table 4.
If I2C-bus bit VIPB = 1, the lower bits of the digitized input signal are connected to
these outputs, congured by the I2C-bus control signals MODE3 to MODE0
SDA
23
I/O
serial data input/output (I2C-bus) 5 V-compatible
SCL
24
I
serial clock input (I2C-bus) 5 V-compatible
RTCO
25
(I/)O
real-time control output: contains information about actual system clock frequency,
eld rate, odd/even sequence, decoder status, subcarrier frequency and phase and
PAL sequence (see external document
“RTC Functional Description”, available on
request); the RTCO pin is enabled via I2C-bus bit OERT; this pin is also used as an
input pin for test purposes and has an internal pull-down resistor; do not
connect any pull-up resistor to this pin
RTS0
26
(I/)O
real-time signal output 0: multi functional output, controlled by I2C-bus bits
RTSE03 to RTSE00; see Table 49. RTS0 is strapped during power-on or CE driven
reset, denes which I2C-bus slave address is used; 0 = 48H for write, 49H for read,
external pull-down resistor of 3.3 k
is needed; 1 = 4AH for write, 4BH for read,
default slave address (default, internal pull-up)
RTS1
27
I/O
real-time signal I/O terminal 1: multi functional output, controlled by I2C-bus bit
RTSE13 to RTSE10; see Table 50
VSSDI
28
P
ground for internal digital core supply
VDDDI
29
P
internal core supply (+3.3 V)
VSSDA
30
P
digital ground for internal crystal oscillator
XTAL
31
O
second terminal of crystal oscillator; not connected if external clock signal is used
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