參數(shù)資料
型號(hào)： 935261790112
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： 5.30 MM, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 2/31頁(yè)
文件大小： 199K
代理商： 935261790112
2000 Feb 04
10
Philips Semiconductors
Preliminary specication
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
L3 mode
The UDA1344TS is set to the L3 mode by setting both
pins MC1 and MC2 to LOW level.
The static pins in this mode are used for:
ADC output overload detection
L3 interface signal input
ADC input voltage selection.
The controllable features via the L3 interface and the
definition of the control registers are given in
Section “L3 interface”.
PINNING DEFINITION
The pinning definition in the L3 mode is given in Table 11.
Table 11 Pinning denition in L3 mode
ADC OUTPUT OVERLOAD DETECTION
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than
1 dB (actual figure is 1.16 dB) of the maximum
possible digital swing. When this condition is detected
pin MP1 is forced to HIGH level for at least 512fs cycles
(11.6 ms at fs = 44.1 kHz). This time-out is reset for each
infringement.
ADC INPUT VOLTAGE SELECTION
In the L3 mode pin MP5 is used to select 0 or 6 dB gain.
Table 12 Levels for pin MP5
PIN
FUNCTION
MP1
ADC output overload detection
MP2
L3MODE input
MP3
L3CLOCK input
MP4
L3DATA input
MP5
ADC input voltage selection:
1 V (RMS) or 2 V (RMS)
PIN MP4
SELECTION
LOW
0 dB gain
HIGH
6 dB gain
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