參數(shù)資料
型號: 935261790112
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝: 5.30 MM, PLASTIC, SSOP-28
文件頁數(shù): 29/31頁
文件大?。?/td> 199K
代理商: 935261790112
2000 Feb 04
7
Philips Semiconductors
Preliminary specication
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output on pin DATAO is held
at LOW level until valid data is available from the
decimation filter. This time depends on whether the
DC-cancellation filter is selected:
DC cancel off:
; t = 23.2 ms at fs = 44.1 kHz
DC cancel on:
; t = 279 ms at fs = 44.1 kHz.
Interpolation lter (DAC)
The digital filter interpolates from 1fs to 128fs by means of
a cascade of a recursive filter and an FIR filter.
Table 4
Interpolation lter characteristics
Noise shaper (DAC)
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSDAC).
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
ITEM
CONDITIONS
VALUE (dB)
Pass-band ripple
0
0.45fs
±0.03
Stop band
>0.55fs
50
Dynamic range
0
0.45f
s
108
Gain
DC
3.5
t
1024
f
s
-------------
=
t
12288
f
s
----------------
=
Multiple format input/output interface
The UDA1344TS supports the following data input/output
formats:
I2S-bus format with data word length of up to 20 bits
MSB-justified serial format with data word length of up to
20 bits
LSB-justified serial format with data word lengths of
16, 18 or 20 bits (in L3 mode only)
Combined data formats:
– L3 mode: MSB-justified data output and
LSB-justified 16, 18 and 20 bits data input
– Static pin mode: MSB-justified data output and
LSB-justified 16 and 20 bits data input.
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
Control mode selection
The UDA1344TS can be used under L3 microcontroller
interface control or static pin control. The mode can be set
via the mode control pins MC1 and MC2 (see Table 5).
Table 5
Mode control pins
Important: in the L3 mode the UDA1344TS is completely
pin and function compatible with the UDA1340M.
PIN MC2
PIN MC1
MODE
LOW
L3 mode
LOW
HIGH
Test mode
HIGH
LOW
HIGH
Static pin mode
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