- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄36334 > 935262922557 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP160 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935262922557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 12/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935262922557 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)
1998 Apr 09
109
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 94 Overview of peak data rates for non-increment (burst) block transfer congurations at 33 MHz PCI clock
Note
1. These peak data rates could be reached for transfers with large BLOCKLENGTH settings, in a well performing
PCI-bus system with low bus load and an appropriate target system without cycle stretching or interrupts.
2. No cycle stretching by RDY/DTACK possible.
PROTOCOL
MODE
TIMEOUT
VALUE
WORD
WIDTH
FAST
MODE
TRANSFER
DIRECTION
TARGET SIDE
PEAK DATA
RATE
OVERALL
PEAK DATA
RATE(1)
Intel/Motorola(2)
0
16 bit
enabled
R/W
33 Mbytes/s
23.0 Mbytes/s
Intel/Motorola(2)
0
8 bit
enabled
R/W
16.5 Mbytes/s
13.5 Mbytes/s
Intel/Motorola
1
16 bit
enabled
R/W
22 Mbytes/s
17.0 Mbytes/s
Intel/Motorola
3
16 bit
enabled
R/W
13.2 Mbytes/s
11.2 Mbytes/s
Intel/Motorola(2)
0
16 bit
disabled
R/W
22 Mbytes/s
17.0 Mbytes/s
Intel/Motorola
1
16 bit
disabled
R/W
16.5 Mbytes/s
13.5 Mbytes/s
It is possible to halt an actual block transfer by external
interrupt. This is achieved by setting the XIRQ_EN bit in
the DEBI_CONFIG register and asserting the GPIO3 pin
input to LOW while an block transfer is active. If the
XRESUME bit is set to 0, this will end the current block
transfer within the next two Dwords. When XRESUME = 1
the transfer will go to a wait state, but the transfer
operation will not end (DEBI_ACTIVE still asserted). When
GPIO3 is de-asserted to HIGH the block transfer will
resume. The contents of DEBI_AD and DEBI_COMMAND
registers are steadily updated on actual address and block
length values during block transfer. Due to this it is
possible to abort the transfer, read back actual status, do
other transfers and resume later with the saved
information. It should be noted that after a Dword aligned
read block transfer (i.e. if
BLOCKLENGTH [1:0] + A16 [1:0] = 4 or A16 [1:0] = 0) the
read back value of the DEBI_AD register points to the
consecutive address of the just filled PCI memory range.
After a Dword unaligned transfer the read back DEBI_AD
value points 1 Dword further (it should be noted that this
also effects the value of the remaining BLOCKLENGTH
after interrupt; A16 target address read back is not effected
by this). RPS is able to react on the GPIO3 pin events.The
16 AD lines are set to 3-state while DEBI is in XIRQ wait
state (XRESUME enabled). To support target devices of
different endian type the swap register has to be
configured.
Fig.37 Endian swapping.
handbook, full pagewidth
3210
2301
3210
4-byte swap
the four bytes in a double word
are swapped
2-byte swap
the two bytes in a 2-byte word
are swapped
0123
MHB069
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935242220551 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935242220557 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935260698551 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935260698557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935260699551 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。