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| 型號(hào)： | 935262922557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 134/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935262922557 |
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1998 Apr 09
87
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.12.4
BRS PROGRAMMING REGISTER
The BRS programming has in principle three modes:
1. Inbound and downscaling: the binary ratio scaler input multiplexer selects data from the Dual D1 real time video
interface, Port A or B and ‘normally’ writes the result via FIFO 3 and DMA3 to PCI, if DMA3 is enabled in master write
mode and not used for other purposes. Syncs including Field ID are taken from Port A or B (FID defines which base
address is used in DMA3).
2. Outbound and upscaling in direct and line memory mode: the binary ratio scaler takes the data from FIFO 3.
The DMA3 is in master read operation. The scaling result can be selected by the DD1 port output multiplexers.
The timing reference signals (VS, HS, LLC and FID) are taken from Port A or B.
3. Outbound and upscaling in field memory mode: the binary ratio scaler takes the data from FIFO 3. The DMA3 is
in master read operation. The scaling result can be selected by the DD1 port output multiplexers. The vertical sync
signal is taken from the VS_A or VS_B port as timing reference signal. At the HS_A or HS_B port the SAA7146A
generates a reset signal for each field. The PXQ is an output signal which is connected to the write enable port of
the memory. If an interlaced source is selected (different base addresses for ODD and EVEN fields), the field
detection must be set to ‘free toggle’ mode, due to the missing horizontal sync signal.
Table 69 BRS control register
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
INBOUND
OUTBOUND
58
BRSdatasel
and MODE
31 and 30
RW
source select for BRS video data:
00: video data stream from A
11: read from DMA_3/FIFO 3
01: video data stream from B
10: reserved
BRSsyncsel
29
RW
source select for BRS sync signals:
0: take Ha, Va, Fa, LLC_A as
select in the ‘Initial setting of
Dual D1 Interface’;
see Table 66.
in direct and line memory mode
the same setting as in the
inbound mode is select
1: take Hb, Vb, Fb, LLC_B as
select in the ‘Initial Setting of
Dual D1 Interface’;
see Table 66.
in eld memory mode the
horizontal sync port must set to
output to get the a eld RESET
signal for a eld memory
BYO
28 to 19
RW
vertical offset, counted in lines,
after selected vertical sync edge
until data is captured from DD1
BYO denes a vertical offset,
counted in lines, after selected
vertical sync-edge until data is
read from the FIFO. For eld
memory mode BYO must be
000H. The video window is
selected by ‘NumLines’,
‘NumBytes’, ‘pitch’ and ‘base
address’.
BRS_V
18 and 17
RW
vertical downscaling:
vertical upscaling:
00: write every line to DMA3
00: regular read
01: write every 2nd line only
01: read every line twice
10: reserved
11: write every 4th line only
11: read every line 4 times
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