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參數(shù)資料
| 型號： | 935262922557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁數(shù)： | 62/147頁 |
| 文件大?。?/td> | 526K |
| 代理商： | 935262922557 |
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1998 Apr 09
21
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.2.2
VIDEO DMA CONTROL
The SAA7146A’s DMA control is able to support up to
three independent video targets or sources respectively.
For this purpose it provides three video DMA channels.
Each channel consists of a FIFO, a FIFO Input Control
(FINC) placed on the video side of the FIFO, and a FIFO
Control (FICO) placed on the PCI side of the FIFO.
Channel 1 only supports the unidirectional data stream
into the PCI memory. It is not able to read data from
system memory. However, this access is possible using
Channels 2 or 3. Table 2 surveys the possibilities and
purposes of each video DMA channel.
Each FIFO, i.e. each DMA channel, has its own
programming set including base address (doubled for odd
and even fields), pitch, protection address, page table
base address, several handling mode control bits and a
transfer enable bit (TR_E). In addition, each channel has a
threshold and a burst length definition for internal
arbitration (see Table 6, Section 7.2.5).
To handle the reading modes FIFO 2 and FIFO 3 offer
some additional registers: Number of Bytes per line
(NumBytes), Number of Lines per field (NumLines) and
the vertical scaling ratio (only FIFO 3, see Table 69).
The programming sets could be reloaded after the
previous job is done [Video Transfer Done (VTD)] to
support several DMA targets per FIFO. The programming
set currently used is loaded by the Register Programming
Sequencer (RPS). If the RPS is not used, the registers
could be rewritten each time, using the SAA7146A as a
slave. But then the programmer must take care of the
synchronization of these write accesses.
All registers needed for DMA control are described in
Table 3, except the transfer enable bits, which are
described in Table 10. The registers are accessed through
PCI base address with appropriate offset (see Table 1).
Table 2
Size, direction and purpose of the video FIFOs and the associated DMA controls
FIFO
SIZE
DIRECTION
PURPOSE
FIFO 1
128 Dwords
write to PCI
FIFO 1 buffers data from the HPS output and writes into PCI memory.
In planar mode FIFO 1 gets the Y data.
FIFO 2
128 Dwords
RW
Planar mode: FIFO 2 buffers U data provided by the HPS; the
associated DMA control 2 sends it into the PCI memory.
Clip mode: DMA control 2 reads clipping information (clip bit mask or
rectangular overlay data) from the PCI system memory and buffers it
in FIFO 2.
FIFO 3
128 Dwords
RW
Planar mode: FIFO 3 buffers V data provided by the HPS and writes
it into the PCI memory.
Chroma keying mode: FIFO 3 buffers chroma keying information
and writes it into PCI memory.
BRS mode: FIFO 3 buffers data provided by the BRS. DMA control 3
sends it into the PCI memory.
Read mode: DMA control 3 reads video data from the PCI system
memory (the same data up to four times to offer a simple upscaling
algorithm) and buffers it in FIFO 3.
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