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參數(shù)資料
| 型號(hào)： | 935263652557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, SOT-393, QFP-64 |
| 文件頁(yè)數(shù)： | 38/75頁(yè) |
| 文件大?。?/td> | 479K |
| 代理商： | 935263652557 |
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1998 May 15
43
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2
I2C-bus detail
The I2C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01
is reserved for chip version.
17.2.1
SUBADDRESS 00
Table 11 Chip version SA00; note 1
Note
1. X = reserved.
17.2.2
SUBADDRESS 02
Table 12 Analog control 1 SA02; note 1
Notes
1. Mode select (see Figs 33 to 40).
2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance
trap bypassed).
Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)
FUNCTION
LOGIC LEVELS
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
Chip version
V1
0001
X
V2
0010
X
FUNCTION(2)
CONTROL BITS D2 TO D0
MODE 2
MODE 1
MODE 0
Mode 0 : CVBS (automatic gain)
0
Mode 1 : CVBS (automatic gain)
0
1
Mode 2 : CVBS (automatic gain)
0
1
0
Mode 3 : CVBS (automatic gain)
0
1
Mode4:Y (automatic gain) + C (gain channel 2 xed to GAI2 level)
1
0
Mode5:Y (automatic gain) + C (gain channel 2 xed to GAI2 level)
1
0
1
Mode6:Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
0
Mode7:Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
DECIMAL VALUE
UPDATE HYSTERESIS FOR 9-BIT GAIN
CONTROL BITS D5 TO D3
GUDL 2
GUDL 1
GUDL 0
0....
off
0
....7
±7 LSB
1
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