參數(shù)資料
型號(hào)： 935285129118
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LED DISPLAY DRIVER, PDSO28
封裝： 4.40 MM, PLASTIC, MO-153, SOT361-1, TSSOP-28
文件頁數(shù)： 35/54頁
文件大?。?/td> 410K
代理商： 935285129118
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PCA9685_2
NXP
B
.V
.2009.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.02
—
16
J
u
ly
2009
40
of
50
NXP
Semiconductor
s
PCA9685
16-c
hannel,
12-bit
PWM
Fm+
I
2C-b
us
LED
contr
oller
[1]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus
time-out feature for DC operation.
[2]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[4]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undened region of SCL’s falling
edge.
[5]
The maximum tf for the SDA and SCL bus lines is specied at 300 ns. The maximum fall time (tf) for the SDA output stage is specied at 250 ns. This allows series protection
resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specied tf.
[6]
Cb = total capacitance of one bus line in pF.
[7]
Input lters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
tPZH
OFF-state to HIGH propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-
40
-
40
-
40
ns
tPLH
LOW to HIGH propagation delay
OE to LEDn;
OUTNE[1:0] = 01
in MODE2 register
-
40
-
40
-
40
ns
tPHL
HIGH to LOW propagation delay
OE to LEDn;
OUTNE[1:0] = 00
in MODE2 register
-
60
-
60
-
60
ns
Table 14.
Dynamic characteristics …continued
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus
Fast-mode Plus
I2C-bus
Unit
Min
Max
Min
Max
Min
Max
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