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參數(shù)資料
| 型號： | 93718CFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 93718 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 96K |
| 代理商： | 93718CFLFT |
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
SEL_DDR = 1 DDR/DDR_SDRAM Outputs VDD=2.5, TA = 0 - 85°C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
IIH
VI = VDD or GND
110
A
Input Low Current
IIL
VI
= V
DD or GND
-100
-25
A
IDD2.5
CL = 0pf, 133MHz
76
200
mA
IDDPD
CL = 0pf, all
310
mA
Output High Current
IOH
VDD = 2.5V
, V
OUT = 1V
-74.5
-18
mA
Output Low Current
IOL
VDD = 2.5V
, V
OUT =
26
42.5
mA
VDD = 2.5V,
VOH = -12mA
VDD = 2.5V
IOH = 12mA
Output differential-pair crossing
voltage
VOC
(VDD/2) –0.1
1.25
(VDD/2) +0.1
V
Input Capacitance
1
CIN
VI = GND or VDD
2pF
1Guaranteed by design, not 100% tested in production.
V
Low-level output voltage
VOL
0.46
2.3
0.35
Operating Supply Current
High-level output voltage
VOH
1.7
SEL_DDR=1 DDR/DDR_SDRAM Outputs = 2.5V, TA = 0 - 85°C (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD3.3_2.5
2.3
2.5
2.7
VDD2.5
2.3
2.5
2.7
Input High Voltage
VIH
SEL_DDR, PD# input
2.0
V
Input Low Voltage
VIL
SEL_DDR, PD# input
0.8
V
Input voltage level
VIN
VDD
V
1Guaranteed by design, not 100% tested in production.
V
Power Supply Voltage
Electrical Characteristics - Input/Supply/Common Output Parameters
Recommended Operating Condition
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