參數資料
型號: 93722CFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 93722 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
封裝: 0.209 INCH, LEAD FREE, MO-150, SSOP-28
文件頁數: 1/7頁
文件大小: 84K
代理商: 93722CFLF
ICS93722
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer
ICS93722
REV F 02/11/07
Low Cost DDR Phase Lock Loop Zero Delay Buffer
DATASHEET
Description
Output Features
DDR Zero Delay Clock Buffer
Low skew, low jitter PLL clock driver
I
2C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
Funtionality Table
Key Specifications
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<110ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
FB_INT
CLK_INT
SCLK
SD
SDA
AT
TA
A
Control
Logic
FB_OUTT
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
PLL
Pin Configuration
28-Pin SSOP
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
N/C
VDDA
GND
VDD
CLKT2
CLKC2
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
N/C
FB_INT
FB_OUTT
N/C
CLKT3
CLKC3
GND
ICS937
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
P
D
V
AT
N
I
_
K
L
CT
K
L
CC
K
L
CT
U
O
_
B
F
V
5
.
2
)
m
o
n
(
LL
H
L
n
o
V
5
.
2
)
m
o
n
(
HH
L
H
n
o
V
5
.
2
)
m
o
n
(
z
H
M
0
2
<Z
Z
f
o
D
N
GL
L
H
L
f
o
/
d
e
s
a
p
y
B
D
N
GH
H
L
H
f
o
/
d
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s
a
p
y
B
Funtional Block Diagram
相關PDF資料
PDF描述
93725AF-T 93725 SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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