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參數(shù)資料
| 型號(hào)： | 954119DFLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 17/19頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | 954119DFLF-T |
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7
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875—05/24/04
I
2C Table: Frequency Select Register
Bit 7
FS Source
Frequency H/W IIC
Select
RW
0
Bit 6
SS_EN1
PLL1 Spread Enable
RW
1
Bit 5
Reserved
RW
1
Bit 4
Bit4
Freq Select Bit 4
RW
0
Bit 3
Bit3
Freq Select Bit 3
RW
0
Bit 2
FSLC
Freq Select Bit 2
RW
Latch
Bit 1
FSLB
Freq Select Bit 1
RW
Latch
Bit 0
FSLA
Freq Select Bit 0
RW
Latch
I
2C Table: Output Control Register
Bit 7
PCICLK_F0
Output Control
RW
1
Bit 6
DOTT/C_96MHz
Output Control
RW
1
Bit 5
USB_48MHz
Output Control
RW
1
Bit 4
REF0
Output Control
RW
1
Bit 3
REF1
Output Control
RW
1
Bit 2
CPUCLKT/C1
Output Control
RW
1
Bit 1
CPUCLKT/C0
Output Control
RW
1
Bit 0
CPUCLK's
PD Mode Output State
Control
RW
0
I
2C Table: Output Control Register
Bit 7
PCICLK5
Output Control
RW
1
Bit 6
PCICLK4
Output Control
RW
1
Bit 5
PCICLK3
Output Control
RW
1
Bit 4
PCICLK2
Output Control
RW
1
Bit 3
PCICLK1
Output Control
RW
1
Bit 2
PCICLK0
Output Control
RW
1
Bit 1
PCICLK_F2
Output Control
RW
1
Bit 0
PCICLK_F1
Output Control
RW
1
I
2C Table: Output Control Register
Bit 7
PCIEXCLK's
PD Mode Output State
Control
RW
0
Bit 6
Reserved
RW
1
Bit 5
PCIEXCLKT/C4
Output Control
RW
1
Bit 4
PCIEXCLKT/C3
Output Control
RW
1
Bit 3
SRCCLKT/C
Output Control
RW
1
Bit 2
PCIEXCLKT/C2
Output Control
RW
1
Bit 1
PCIEXCLKT/C1
Output Control
RW
1
Bit 0
PCIEXCLKT/C0
Output Control
RW
1
I
2C Table: Output Control Register
Bit 7
PCI/SRC Stop EN
Stop all PCI / PCIEX /
SRC clocks
1
Bit 6
PCICLK_F2
Stop Control
RW
0
Bit 5
PCICLK_F1
Stop Control
RW
0
Bit 4
PCICLK_F0
Stop Control
RW
0
Bit 3
PCIEXCLKT/C (5:3)
Stop Control
RW
1
Bit 2
SRCCLKT/C
Stop Control
RW
1
Bit 1
PCIEXCLKT/C (2:0)
Stop Control
RW
1
Bit 0
Reserved
RW
1
--
-
Free Running
Stoppable
Free Running
Stoppable
Free Running
Stoppable
-
Free Running
Stoppable
PWD
Enable
Disable
-
Free Running
Stoppable
Name
Control Function
Type
1
Disable
Enable
18,17
Disable
Enable
Disable
Enable
24,23
Disable
Enable
Disable
Enable
Disable
Enable
PWD
Driven
Hi-Z
--
Disable
Enable
Byte 3
Pin #
Name
Control Function
Type
0
1
Disable
Enable
9
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
1PWD
Disable
Enable
Name
Control Function
Type
0
Disable
Enable
-
Driven
Hi-Z
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
PWD
Disable
Enable
Disable
Enable
See Table 1: PLL 1 Frequency Selection Table
-
Byte 1
Pin #
Name
Control Function
Type
0
1
-
OFF
ON
--
1PWD
Latch Inputs
IIC
Name
Control Function
Type
0
14,15
12
-
Pin #
-
7
27,26
-
0
Free Running
Byte 2
Pin #
40,39
43,42
51
50
53
55
-
33,32
31,30
-
Byte 0
Pin #
54
-
4
3
2
8
22,21
Byte 4
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