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| 型號(hào)： | 954119DFLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | 954119DFLF-T |
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15
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875—05/24/04
Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
1
Clock period
T
period
48.00MHz output nominal
20.8313
20.8354
ns
Output Impedance
R
DSP
V
O = VDD*(0.5)
12
55
1
Output High Voltage
V
OH
I
OH = -1 mA
2.4
V
1
Output Low Voltage
V
OL
I
OL = 1 mA
0.55
V
1
V
OH @MIN = 1.0 V
-33
mA
1
V
OH@MAX = 3.135 V
-33
mA
1
V
OL @ MIN = 1.95 V
30
mA
1
V
OL @ MAX = 0.4 V
38
mA
1
Edge Rate
t
slewr/f
Rising/Falling edge rate
1
4
V/ns
1
Edge Rate
t
slewr/f_USB
USB48 Rising/Falling edge rate
1
2
V/ns
1
Rise Time
t
r
V
OL = 0.4 V, VOH = 2.4 V
0.5
2
ns
1
Fall Time
t
f
V
OH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
Rise Time
t
r_USB
V
OL = 0.4 V, VOH = 2.4 V
1
2
ns
1
Fall Time
t
f_USB
V
OH = 2.4 V, VOL = 0.4 V
1
2
ns
1
Duty Cycle
d
t1
V
T = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T = 1.5 V
500
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7
(Rs is used in USB48MHz test only)
1Guaranteed by design and characterization, not 100% tested in production.
Output High Current
I
OH
Output Low Current
I
OL
Electrical Characteristics - DOT_96MHz 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
Current Source Output
Impedance
Zo
V
O = Vx
3000
1
Voltage High
VHigh
660
850
mV
1,3
Voltage Low
VLow
-150
150
mV
1,3
Max Voltage
Vovs
1150
mV
1
Min Voltage
Vuds
-300
mV
1
Crossing Voltage (abs)
Vx(abs)
250
550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
140
mV
1
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
1,2
Average period
Tperiod
96.00MHz nominal
10.4135
10.4198
ns
2
Absolute min period
Tabsmin
96.00MHz nominal
10.1635
ns
1,2
Rise Time
t
r
V
OL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
t
f
V
OH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-t
r
V
OL = 0.175V, VOH = 0.525V
125
ps
1
Fall Time Variation
d-t
f
V
OH = 0.525V VOL = 0.175V
125
ps
1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45
55
%
1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
250
ps
1
*T
A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, ΙREF = 475
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3I
REF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
Measurement on single ended
signal using absolute value.
Statistical measurement on
single ended signal
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